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w83795g/adg nuvoton h/w monitor date: aug/2/2010 revision: 1.41
w83795g/adg - ii ? aug/2/2010 revision 1.41 table of content- 1. general descri ption (w83795g)...................................................................................... 4 2. general descript ion (w83795a dg)................................................................................. 5 3. features (w 83795g) ............................................................................................................. 6 monitori ng items ............................................................................................................. 6 address resolution protocol and alert st andard format............................................... 7 alarm ou tput................................................................................................................... 7 general ........................................................................................................................ ... 7 package ........................................................................................................................ .. 7 4. features (w 83795adg) ........................................................................................................ 8 monitori ng items ............................................................................................................. 8 address resolution protocol and alert st andard format............................................... 9 alarm ou tput................................................................................................................... 9 general ........................................................................................................................ ... 9 package ........................................................................................................................ .. 9 5. key specific ations ............................................................................................................ 10 6. pin config uration ............................................................................................................. 11 7. pin descri ption................................................................................................................... 13 7.1 pin type desc ription..................................................................................................... 13 7.2 w83795g pin desc ription list...................................................................................... 13 7.3 W83795ADG pin de scripti on li st................................................................................. 21 8. register summa ry ? bank0 ............................................................................................ 28 8.1 id, bank select registers............................................................................................. 30 8.2 configuration and address select r egisters................................................................ 32 8.3 multi-function pin control r egisters ............................................................................ 34 8.4 watch dog time r registers.......................................................................................... 40 8.4.1 watch dog timer r egister deta ils........................................................................... 42 8.5 voltage/temperature/fani n reading r egisters ......................................................... 43 8.5.1 voltage channel re gister deta ils ............................................................................ 44 8.5.2 fan register details ................................................................................................ 48 8.6 smi# control and st atus regi sters .............................................................................. 49 8.6.1 smi control/status register map ............................................................................ 50 8.7 ovt and beep contro l registers ................................................................................ 54 8.7.1 beep/ovt control re gisters deta ils ...................................................................... 55 8.8 thermtrip and prochot control r egisters.......................................................... 59 8.9 vid control and st atus registers................................................................................. 67 8.10 voltage/temperature/fanin limitation r egisters ....................................................... 69 8.11 temperature sensors offset registers ........................................................................ 78 9. register summa ry ? bank1 ............................................................................................ 80 9.1 asf control registers .................................................................................................. 80 9.1.2 asf register deta ils ............................................................................................... 85 10. register summa ry ? bank2 ............................................................................................ 95
w83795g/adg - iii ? aug/2/2010 revision 1.41 10.1.2 fan register details .............................................................................................. 102 11. peci control and sb -tsi fu nction ............................................................................ 118 11.1 peci control registers............................................................................................... 118 11.2 sb temperature sensor interface (sb-tsi)............................................................... 121 12. register summa ry ? bank3 .......................................................................................... 123 12.1 digital temperature sensor configuration (dtsc) .................................................... 124 12.2 digital temperature se nsor enabl e (dtse) .............................................................. 124 12.3 peci control regi ster (pcr) ..................................................................................... 126 12.4 waiting available time for peci 1.1 only (watp) ..................................................... 127 12.5 peci agent configurati on registers (pac)................................................................. 127 12.6 peci report temperature style regist ers (prts) ..................................................... 128 12.7 peci manual mode contro l register s (pmmc ) ......................................................... 129 12.8 peci agent tbase temperat ure register s (patb)..................................................... 131 12.9 getdib comm and (gdc) ........................................................................................... 132 12.10 agent characteristic register s (acr) ...................................................... 133 12.11 agent relative temperat ure register s (artr) ....................................... 134 12.12 agent tcontrol temperat ure register s (attr)........................................ 136 12.13 pci configuration addr ess registers (pcar).......................................... 137 12.14 pci configuration wr ite data (pcwd) ..................................................... 138 12.15 pci configuration read data (pcrd)...................................................... 139 12.16 mbxsend comm and (msc)...................................................................... 139 12.17 completion code (cc).............................................................................. 140 12.18 mbxget comm and (mgc ) ........................................................................ 140 12.19 sb-tsi configuration register (stcr) .................................................... 141 12.20 sb-tsi auto read period (starp).......................................................... 142 12.21 sb-tsi slave e nable (s tse) ................................................................... 142 12.22 sb-tsi one shot start register (stoss) ................................................. 143 12.23 sb-tsi manual mode configur ation registers (stmmcr)...................... 143 12.24 sb-tsi read da ta (strd) ....................................................................... 145 13. electrical cha racteristics....................................................................................... 146 13.1 absolute maxi mum ratings ........................................................................................ 146 13.2 dc characte ristics ...................................................................................................... 146 13.3 ac characteristics ...................................................................................................... 148 clock input timing ............................................................................................................. ....... 148 14. order info rmation ......................................................................................................... 149 15. top marking spec ifications........................................................................................ 150 16. package drawing an d dimens ions............................................................................ 151 17. revision histor y .............................................................................................................. 153
w83795g/adg - 4 ? aug/2/2010 revision 1.41 1. general description (w83795g) w83795g is an evolving version of the nuvoton popular hardware monitor ic family. w83795g provides several innovative features, such as asf 2.0 compliant specification, smbus 2.0 arp compatible command, intel peci2.0 interface, amd sb-tsi interface, processor hot, parallel vid input, and serial vid input. conventionally, w83795g can be used to monitor several critical hardware parameters of the system, including power supply vo ltages, fan speeds, and temperatures, which are very important for a high-end computer system, such as server, workstation?etc, to work stably and efficiently. a 10-bit analog-to-digital converter (adc) is built inside w83795g. w83795g can simultaneously monitor 15 (up to 21) analog volt age inputs (including power vdd / 3vsb / vbat / vtt monitoring), 8 (up to 14) fan tachometer inputs, 8 fan output control, 6 remote temperature sensor inputs, 4 of which support current mode (dual current source) temper ature measurement method, caseopen detection, watch dog timer function, and gpio pins. the sense of remote temperature can be performed by thermistors, or directly from intel? / amd tm cpu with thermal diode output. w83795g provides 8 pwm (pulse width modulation) / dc fan output modes for s mart f an tm control - s thermal cruise tm t mode and s s mart f an tm iv t mode. under s thermal cruise tm t mode, temperatures of cpu and the system can be maintained within specific prog rammable ranges under the hardware control. as for s mart f an tm iv, which provides 8 sets of temperatures setting point each could control fan?s duty cycle, depends on this construction, fan could be operated at the lowest pos sible speed so that the acoustic noise could be balanced. as for warning mechanism, w83795g provides smi#, ovt#, volt_fault#, fan_fault#, and beep signals to prot ect the system. w83795g has 2 specific pins to provide address selection so that 4 w83795g could be wired through i 2 c interface at the same time. w83795g can uniquely serve as an asf sensor to respond to asf master?s request for the implementation of network management in os-absent status. through w83795g?s compliance with asf2.0 sensor specification, network server is able to monitor the env ironmental status of each client in os-absent state by pet (platform event trap) frame values returned from w83795g, such as temperatures, voltages, fan speed and case open. moreover, w83795g supports smbus 2.0 arp command to solve the problem of address conflicts by dynamically assigning a new unique address for w83795g asf function after w83795g?s udid is sent. through the application software or bios, the users can read all the monitored parameters of the system from time to time. a pop-up warning can also be activated when the monitored item is out of the proper/preset range. the application software could be nuvoton's hardware doctor tm or other management application software. besides, the user s can set up the upper and lower limits (alarm thresholds) of these monitored parameters an d activate corresponding maskable interrupts.
w83795g/adg - 5 ? aug/2/2010 revision 1.41 2. general description (W83795ADG) W83795ADG is an evolving version of the nuvoton popular hardware monitor ic family. W83795ADG provides several innovative features, such as asf 2.0 compliant specification, smbus 2.0 arp compatible command, intel peci2.0 interface, and processor hot. conventionally, W83795ADG can be used to monitor several critic al hardware parameters of the system, including power supply voltages, fan speeds, and temperatur es, which are very important for a high-end computer system, such as server, workstat ion?etc, to work stably and efficiently. a 10-bit analog-to-digital converter (adc) is built inside W83795ADG. W83795ADG can simultaneously monitor 12 (up to 18) analog voltage inputs (including power vdd / 3vsb / vbat / vtt monitoring), 8 (up to 14) fan tachometer inputs, 2 fan output control, 6 remo te temperature sensor inputs, 4 of which support current mode (dual cu rrent source) temperatur e measurement method, caseopen detection, watch dog timer function, and gpio pins. the sense of remote temperature can be performed by thermistors, or directly from intel? cpu with thermal diode output. W83795ADG provides 2 pwm (pulse width modul ation) / dc fan output modes for s mart f an tm control - s thermal cruise tm t mode and s s mart f an tm iv t mode. under s thermal cruise tm t mode, temperatures of cpu and the system can be maintained within sp ecific programmable ranges under the hardware control. as for s mart f an tm iv, which provides 8 sets of temper atures setting point each could control fan?s duty cycle, depends on this co nstruction, fan could be operated at the lowest possible speed so that the acoustic noise could be balanced. as fo r warning mechanism, W83795ADG provides smi#, ovt#, and beep signals to protect the system. w83795a dg has 2 specific pi ns to provide address selection so that 4 W83795ADG could be wired through i 2 c interface at the same time. W83795ADG can uniquely serve as an asf sensor to respond to asf master?s request for the implementation of network management in os-absent status. through W83795ADG?s compliance with asf2.0 sensor specification, network server is able to monitor the env ironmental status of each client in os-absent state by pet (platform event trap) frame values returned from W83795ADG, such as temperatures, voltages, fan speed and case open. moreover, W83795ADG supports smbus 2.0 arp command to solve the problem of address conflicts by dynamically assigning a new unique address for W83795ADG asf function after W83795ADG?s udid is sent. through the application software or bios, the users can read all the monitored parameters of the system from time to time. a pop-up warning can also be activated when the monitored item is out of the proper/preset range. the application software could be nuvoton's hardware doctor tm or other management application software. besides, the user s can set up the upper and lower limits (alarm thresholds) of these monitored parameters an d activate corresponding maskable interrupts.
w83795g/adg - 6 ? aug/2/2010 revision 1.41 3. features (w83795g) ? monitoring items voltage up to 21 voltage sensing inputs. z 11 general voltage inputs. z 4 power pins. z 2 multi-function with thermistor temperature inputs. z 4 multi-function with thermal diode pair. vid z provide parallel vid input and serial vid (amd tm ) input monitoring. temperature up to 6 temperature monitoring. z 4 pairs thermal diode (current mode) temperature. z 2 thermistor mode temperature. z support intel? peci interfaces for readi ng cpu temperature. (including peci_req# mechanism) z support amd tm sb-tsi for reading cpu temperature peci (platform environment control interface) z support peci 2.0 specification z support 8 cpu address and 2 domains per cpu address amd tm sb-tsi interface z support amd tm sb-tsi specification fan up to 8 fan control output and up to 14 fan tachometer input. z 6 pure fan control output pins (pwm / dc mode supported). z 2 fan control output multi-function (fanctl7 and fanctl8). z 8 pure fan tachometer input (fanin1-fanin8). z 5 fan tachometer input multi-function (fanin9-fanin14) smart fan tm control
w83795g/adg - 7 ? aug/2/2010 revision 1.41 z support the s mart f an tm control ? ?thermal cruise tm ? mode and ?s mart f an tm iv? mode. z multi-temperature source vs. multi-fan-control output. z 6 mapping table for temperature vs. fan c ontrol output (based on temperature?s behavior). z 8 tables for speed cruise mode for fan control output. z item 2 and item 3 could both control fan control output behavior. caseopen z case open detection input. (low active). ? address resolution protocol and alert standard format z support system management bus (smbus) version 2.0 specification. z comply with hardware sensor slave arp (address resolution protocol). z response asf 2.0 command -- get event data, get event status, device type poll. z comply with asf 2.0 sensors (monitoring fan speed, voltage, temperature, thermal trip and case open event/status). z support remote control subset: remote power-on/ power-off/ reset. ? alarm output z issue smi#, ovt#, volt_fault#, fan_fault# signals to activate system protection. z issue beep signal to activate system speaker or buzzer. ? general z provide up to 8 gpio pins (multi-function with parallel vid). z i 2 c / smbus2.0 serial bus interface (max. 400khz clock). z watch dog timer function: wdtrst#, sysrst_in. z 2 address selection pins provide selectable address settings for application of 4 w83795g wired together through i 2 c interface. z 3.3v operation. ? package z 64-lqfp package type z pb-free / rohs-compliant
w83795g/adg - 8 ? aug/2/2010 revision 1.41 4. features (W83795ADG) ? monitoring items voltage up to 18 voltage sensing inputs. z 8 general voltage inputs. z 4 power pins. z 2 multi-function with thermistor temperature inputs. z 4 multi-function with thermal diode pair. temperature up to 6 temperature monitoring. z 4 pairs thermal diode (current mode) temperature z 2 thermistor mode temperature. z support intel? peci interfaces for readi ng cpu temperature. (including peci_req# mechanism). peci (platform environment control interface) z support peci 2.0 specification z support 8 cpu address and 2 domains per cpu address fan up to 2 fan control output and up to 14 fan tachometer input. z 2 pure fan control output pins (pwm / dc mode supported). z 8 pure fan tachometer input (fanin1-fanin8). z 5 fan tachometer input multi-function (fanin9-fanin14). smart fan tm control z support the s mart f an tm control ? ?thermal cruise tm ? mode and ?s mart f an tm iv? mode. z multi-temperature source vs. multi-fan-control output. z 6 mapping table for temperature vs. fan c ontrol output (based on temperature?s behavior). z 8 tables for speed cruise mode for fan control output. z item 2 and item 3 could both control fan control output behavior. caseopen z case open detection input. (low active).
w83795g/adg - 9 ? aug/2/2010 revision 1.41 ? address resolution protocol and alert standard format z support system management bus (smbus) version 2.0 specification. z comply with hardware sensor slave arp (address resolution protocol). z response asf 2.0 command -- get event data, get event status, device type poll. z comply with asf 2.0 sensors (monitoring fan speed, voltage, temperature, thermal trip and case open event/status). z support remote control subset: remote power-on/ power-off/ reset. ? alarm output z issue smi# and ovt# signals to activate system protection. z issue beep signal to activate system speaker or buzzer (multi-function with ovt#) ? general z provide up to 4 gpio pins (multi-function with fanin). z i 2 c / smbus2.0 serial bus interface (max. 400khz clock). z watch dog timer function: wdtrst#, sysrst_in. z 2 address selection pins provi de selectable address settings for application of 4 W83795ADG wired together through i 2 c interface. z 3.3v operation. ? package z 48-lqfp package type z pb-free / rohs-compliant
w83795g/adg - 10 ? aug/2/2010 revision 1.41 5. key specifications z voltage monitoring accuracy 10mv z temperature sensor accuracy remote diode sensor accuracy (25~90 c) 1 c typ. resolution 0.25 : z supply voltage 3vdd and 3vsb 3.3v 10% z operating supply current 15 ma typ.
w83795g/adg - 11 ? aug/2/2010 revision 1.41 6. pin configuration w83795g w83794g 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vref agnd vsen12/tr5 vsen13/tr6 vdsen14-/tr1-/d1- vdsen15+/tr2+/d2+ vdsen15-/tr2-/d2- vdsen16+/tr3+/d3+ vdsen16-/tr3-/d3- vdsen17+/tr4+/d4+ vdsen17-/tr4-/d4- (vdd0/vcore1)vsen1 (vdd1/vcore2)vsen2 (vddnb/vcore3)vsen3 vsen4 clkin sysrstin#/fanin13/prochot3# sda_tsi/thermtrip# peci/scl_tsi vtt caseopen# vbat 3vsb 3vdd vsen11 vsen10 vsen9 vsen8 vsen7 vsen6 vsen5 fanin5 fanctl4 fanin4 fanctl3 fanin3 fanctl2/addr1 fanin2 fanclt1/addr0 fanin1 wdtrst#/prochot2# pwrbtn#/prochot1# beep ovt# smi#/fanin14/prochot4# sda scl fanctl5 fanin6 fanctl6 fanin7 prochot1#/fanctl7 fanin8 prochot2#/fanctl8 gnd fanin9/pvid0/gpio1 fanin10/pvid1/gpio2 fanin11/peci_req#/pvid2/gpio3 fanin12/pvid3/gpio4 volt_fault#/pvid4/gpio5 fan_fault#pvid5/gpio6 ovt2#/scl_svi/pvid6/gpio7 ovt3#/sda_svi/pvid7/gpio8 w83795g 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vdsen14+/tr1+/d1+
w83795g/adg - 12 ? aug/2/2010 revision 1.41 W83795ADG W83795ADG 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 vsen13/tr6 vdsen14+/tr1+/d1+ vdsen14-/tr1-/d1- vdsen15+/tr2+/d2+ vdsen15-/tr2-/d2- vdsen16+/tr3+/d3+ vdsen16-/tr3-/d3- vdsen17+/tr4+/d4+ vdsen17-/tr4-/d4- vsen1 vsen2 vsen3 sysrstin#/fanin13/prochot3# peci vtt caseopen# vbat 3vsb 3vdd vsen8 vsen7 vsen6 vsen5 vsen4 fanin3 fanctl2/addr1 fanin2 fanctl1/addr0 fanin1 wdtrst#/prochot2# pwrbtn#/prochot1# beep/ovt# smi#/fanin14/prochot4# sda scl clkin fanin4 fanin5 fanin6 fanin7 fanin8 gnd fanin9/gpio1 fanin10/gpio2 fanin11/peci_req#/gpio3 fanin12/gpio4 vref vsen12/tr5
w83795g/adg - 13 ? aug/2/2010 revision 1.41 7. pin description 7.1 pin type description symbol description t ttl level v1 type of intelpvid v2 type of amdpvid v3 type of amdsvid v4 type of peci v5 type of prochot s schmitt trigger 12 12ma sink/source capability out output pin od open-drain output pin aout output pin (analog) in input pin (digital) ain input pin(analog) 7.2 w83795g pin description list pin name pin no. power plane type description vref 1 3vsb aout reference voltage output. (2.048v) agnd 2 gnd power ground for analog circuit tr5 thermistor 5 sensing input. (default) vsen12 3 3vsb ain voltage sensing input. detection range is 0~2.048v. tr6 thermistor 6 sensing input. (default) vsen13 4 3vsb ain voltage sensing input. detection range is 0~2.048v. d1+ 5 3vsb ain thermal diode 1 d+. (default)
w83795g/adg - 14 ? aug/2/2010 revision 1.41 pin name pin no. power plane type description tr1+ thermistor 1 sensing input. vdsen14+ voltage sensing input. detection range is 0~2.048v. d1- thermal diode 1 d-. (default) tr1- thermistor 1 sensing input. vdsen14- 6 3vsb ain voltage sensing input, it has to connect to gnd. d2+ thermal diode 2 d+. (default) tr2+ thermistor 2 sensing input. vdsen15+ 7 3vsb ain voltage sensing input. detection range is 0~2.048v. d2- thermal diode 2 d-. (default) tr2- thermistor 2 sensing input. vdsen15- 8 3vsb ain voltage sensing input, it has to connect to gnd. d3+ thermal diode 3 d+. (default) tr3+ thermistor 3 sensing input. vdsen16+ 9 3vsb ain voltage sensing input. detection range is 0~2.048v. d3- thermal diode 3 d-. (default) tr3- thermistor 3 sensing input. vdsen16- 10 3vsb ain voltage sensing input, it has to connect to gnd. d4+ thermal diode 4 d+. (default) tr4+ 11 3vsb ain thermistor 4 terminal input.
w83795g/adg - 15 ? aug/2/2010 revision 1.41 pin name pin no. power plane type description vdsen17+ voltage sensing input. detection range is 0~2.048v. d4- thermal diode 4 d-. (default) tr4- thermistor 4 sensing input. vdsen17- 12 3vsb ain voltage sensing input, it has to connect to gnd. vdd0/vcore1/ vsen1 13 3vsb ain voltage sensing input. detection range is 0~2.048v. when dynamic vid (dvid) function is enable. vcore1 sensing input for pvid or vdd0 sensing input for svid. vdd1/vcore2/ vsen2 14 3vsb ain voltage sensing input. detect range is 0~2.048v. when dynamic vid (dvid) function is enable. vcore2 sensing input for pvid or vdd1 sensing input for svid. vddnb/vcore3/ vsen3 15 3vsb ain voltage sensing input. detect range is 0~2.048v. when dynamic vid (dvid) function is enable. vddnb sensing input for svid. vcore3 sensing input for pvid or vddnb sensing input for svid. vsen4 16 3vsb ain voltage sensing input. detect range is 0~2.048v vsen5 17 3vsb ain voltage sensing input. detect range is 0~2.048v vsen6 18 3vsb ain voltage sensing input. detect range is 0~2.048v vsen7 19 3vsb ain voltage sensing input. detect range is 0~2.048v vsen8 20 3vsb ain voltage sensing input. detect range is 0~2.048v vsen9 21 3vsb ain voltage sensing input. detect range is 0~2.048v vsen10 22 3vsb ain voltage sensing input. detect range is 0~2.048v vsen11 23 3vsb ain voltage sensing input. detect range is 0~2.048v
w83795g/adg - 16 ? aug/2/2010 revision 1.41 pin name pin no. power plane type description 3vdd 24 - power +3v vdd power. it is also a voltage monitor channel. this pin has internal divider resistors to scale down the input voltage for analog voltage measurement. bypass with the parallel combination of 10 f (electrolytic or tantalum) and 0.1 f (ceramic) bypass capacitors. 3vsb 25 - power this pin is power for w83795g. it is also a voltage monitor channel. this pin has internal divider resistors to scale down the input voltage for analog voltage measurement. bypass with the parallel combination of 10 f (electrolytic or tantalum) and 0.1 f (ceramic) bypass capacitors. vbat 26 - power vbat supplies power for caseopen. besides, it is also a voltage monitor channel for +3v on-board battery. this pin has internal divider resistors to scale down the input voltage for analog voltage measurement. caseopen# 27 vbat in ts caseopen detection. an active low input from an external device when chassis is intruded. this signal will be latched even the chassis is closed. vtt 28 vtt power intel? cpu vtt power. it is also a voltage monitor channel. detect range is 0~2.048v peci v4 intel? cpu peci interface. (default) scl_tsi 29 3vsb v3 amd? cpu sb-tsi interface. sda_tsi v3 amd? cpu sb-tsi interface thermtrip# 30 3vsb v5 cpu thermtrip# signal. (default) when cpu assert thermtrip# signal, w83795g will latch this event. sysrstin# in ts system reset input. (default) when this pin is asserted to low, watch-dog timer will be reset. fanin13 in ts fan tachometer input prochot3# 31 3vsb v5 this is a bi-directional pin. as an input signal, when it is pull-ed to low, the
w83795g/adg - 17 ? aug/2/2010 revision 1.41 pin name pin no. power plane type description corresponding fan control output pins will be set to a preset value. clkin 32 3vsb in ts system clock input. peci ,amd-tsi ,vid and fan functions will use this clock to drive logics. scl 33 3vsb in ts i 2 c serial bus clock. sda 34 3vsb in ts / od 12 i 2 c serial bus bi-directional data. smi# od 12 system management interrupt. (default) fanin14 in ts fan tachometer input prochot4# 35 3vsb v5 this is a bi-directional pin. as an input signal, when it is pull-ed to low, the corresponding fan control output pins will be set to a preset value. ovt# 36 3vsb od 12 over temperature alert. low active. beep 37 3vsb od 12 beep output when abnormal event occurs. when this is no abnormal events, this pin asserts high. pwrbtn# od 12 power button output for enable/disable power supply. (default) this pin is related to asf commands. prochot1# 38 3vsb v5 this is a bi-directional pin. as an input signal, when it is pull-ed to low, the corresponding fan control output pins will be set to a preset value. wdtrst# od 12 output signal for system reset. (default) there are two reset sources: watch-dog timer and asf reset command. when reset event occurs, this pin will assert 100ms low pulse for system reset. prochot2# 39 3vsb v5 this is a bi-directional pin. as an input signal, when it is pull-ed to low, the corresponding fan control output pins will be set to a preset value.
w83795g/adg - 18 ? aug/2/2010 revision 1.41 pin name pin no. power plane type description fanin1 40 3vsb in ts fan tachometer input fanctl1 out 12 / aout fan speed control pwm/dc output. when the power of 3vdd is 0v, this pin will drive logic 0. the power of this pin is supplied by 3vsb. it can be configured to pwm/dc mode by registers. default is pwm output. as dc output, 256 steps output voltage scaled to 0~3vsb. addr0 41 3vsb in ts i 2 c device address bit0 trapping during 3vsb power on. fanin2 42 3vsb in ts fan tachometer input fanctl2 out 12 / aout fan speed control pwm/dc output. when the power of 3vdd is 0v, this pin will drive logic 0. the power of this pin is supplied by 3vsb. it can be configured to pwm/dc mode by registers. default is pwm output. as dc output, 256 steps output voltage scaled to 0~3vsb. addr1 43 3vsb in ts i 2 c device address bit1 trapping during 3vsb power on. fanin3 44 3vsb in ts fan tachometer input fanctl3 45 3vsb od 12 / aout fan speed control pwm/dc output. when the power of 3vdd is 0v, this pin will drive logic 0. the power of this pin is supplied by 3vsb. it can be configured to pwm/dc mode by registers. default is pwm output. as dc output, 256 steps output voltage scaled to 0~3vsb. fanin4 46 3vsb in ts fan tachometer input fanctl4 47 3vsb od 12 / aout fan speed control pwm/dc output. when the power of 3vdd is 0v, this pin will drive logic 0. the power of this pin is supplied by 3vsb. it can be configured to pwm/dc mode by registers. default is pwm output. as dc output, 256 steps output voltage scaled to 0~3vsb. fanin5 48 3vsb in ts fan tachometer input
w83795g/adg - 19 ? aug/2/2010 revision 1.41 pin name pin no. power plane type description fanctl5 49 3vsb od 12 / aout fan speed control pwm/dc output. when the power of 3vdd is 0v, this pin will drive logic 0. the power of this pin is supplied by 3vsb. it can be configured to pwm/dc mode by registers. default is pwm output. as dc output, 256 steps output voltage scaled to 0~3vsb. fanin6 50 3vsb in ts fan tachometer input fanctl6 51 3vsb od 12 / aout fan speed control pwm/dc output. when the power of 3vdd is 0v, this pin will drive logic 0. the power of this pin is supplied by 3vsb. it can be configured to pwm/dc mode a by registers. default is pwm output. as dc output, 256 steps output voltage scaled to 0~3vsb. fanin7 52 3vsb in ts fan tachometer input fanctl7 od 12 / aout fan speed control pwm/dc output. (default) when the power of 3vdd is 0v, this pin will drive logic 0. the power of this pin is supplied by 3vsb. it can be configured to pwm/dc mode by registers. default is pwm output. as dc output, 256 steps output voltage scaled to 0~3vsb. prochot1# 53 3vsb v5 this is a bi-directional pin. as an input signal, when it is pull-ed to low, the corresponding fan control output pins will be set to a preset value. fanin8 54 3vsb in ts fan tachometer input fanctl8 55 3vsb od 12 / aout fan speed control pwm/dc output. (default) when the power of 3vdd is 0v, this pin will drive logic 0. the power of this pin is supplied by 3vsb. it can be configured to pwm/dc mode by registers. default is pwm output. as dc output, 256 steps output voltage scaled to 0~3vsb.
w83795g/adg - 20 ? aug/2/2010 revision 1.41 pin name pin no. power plane type description prochot2# v5 this is a bi-directional pin. as an input signal, when it is pull-ed to low, the corresponding fan control output pins will be set to a preset value. gnd 56 power system ground. pvid0 v1/v2 voltage supply readouts bit 0 from cpu. gpio1 ints /od 12 general purpose i/o function. (default) fanin9 57 3vsb in ts fan tachometer input pvid1 v1/v2 voltage supply readouts bit 1 from cpu. gpio2 ints /od 12 general purpose i/o function. (default) fanin10 58 3vsb in ts fan tachometer input pvid2 v1/v2 voltage supply readouts bit 2 from cpu. gpio3 ints /od 12 general purpose i/o function. (default) fanin11 in ts fan tachometer input peci_req# 59 3vsb od 12 peci control signal for cpu entering c3/c4 state. pvid3 v1/v2 voltage supply readouts bit 3 from cpu. gpio4 ints /od 12 general purpose i/o function. (default) fanin12 60 3vsb in ts fan tachometer input pvid4 v1/v2 voltage supply readouts bit 4 from cpu. gpio5 ints /od 12 general purpose i/o function. (default) volt_fault# 61 3vsb od 12 active-low output. this pin will be a logic low when the voltage exceeds its high/low limit.
w83795g/adg - 21 ? aug/2/2010 revision 1.41 pin name pin no. power plane type description pvid5 v1/v2 voltage supply readouts bit 5 from cpu. gpio6 ints /od 12 general purpose i/o function. (default) fan_fault# 62 3vsb od 12 active-low output. this pin will be a logic low when any fan is abnormally stopped. pvid6 v1 voltage supply readouts bit 6 from cpu. gpio7 ints /od 12 general purpose i/o function. (default) ovt2# od 12 over temperature alert. low active scl_svi 63 3vsb v3 amd? cpu svi interface pvid7 v1 voltage supply readouts bit 7 from cpu. gpio8 ints /od 12 general purpose i/o function. (default) ovt3# od 12 over temperature alert. low active sda_svi 64 3vsb v3 amd? cpu svi interface in: monitor sda_svi interface. od 12: response ack command 7.3 W83795ADG pin description list pin name pin no. power plane type description tr6 thermistor 6 sensing input. (default) vsen13 1 3vsb ain voltage sensing input. detection range is 0~2.048v. d1+ 2 3vsb ain thermal diode 1 d+.(default)
w83795g/adg - 22 ? aug/2/2010 revision 1.41 pin name pin no. power plane type description tr1+ thermistor 1 sensing input. vdsen14+ voltage sensing input. detection range is 0~2.048v. d1- thermal diode 1 d-. (default) tr1- thermistor 1 sensing input. vdsen14- 3 3vsb ain voltage sensing input, it has to connect to gnd. d2+ thermal diode 2 d+. (default) tr2+ thermistor 2 sensing input. vdsen15+ 4 3vsb ain voltage sensing input. detection range is 0~2.048v. d2- thermal diode 2 d-. (default) tr2- thermistor 2 sensing input. vdsen15- 5 3vsb ain voltage sensing input, it has to connect to gnd. d3+ thermal diode 3 d+. (default) tr3+ thermistor 3 sensing input. vdsen16+ 6 3vsb ain voltage sensing input. detection range is 0~2.048v. d3- thermal diode 3 d-. (default) tr3- thermistor 3 sensing input. vdsen16- 7 3vsb ain voltage sensing input, it has to connect to gnd. d4+ thermal diode 4 d+. (default) tr4+ 8 3vsb ain thermistor 4 terminal input.
w83795g/adg - 23 ? aug/2/2010 revision 1.41 pin name pin no. power plane type description vdsen17+ voltage sensing input. detection range is 0~2.048v. d4- thermal diode 4 d-. (default) tr4- thermistor 4 sensing input. vdsen17- 9 3vsb ain voltage sensing input, it has to connect to gnd. vsen1 10 3vsb ain voltage sensing input. detection range is 0~2.048v. vsen2 11 3vsb ain voltage sensing input. detect range is 0~2.048v. vsen3 12 3vsb ain voltage sensing input. detect range is 0~2.048v. vsen4 13 3vsb ain voltage sensing input. detect range is 0~2.048v vsen5 14 3vsb ain voltage sensing input. detect range is 0~2.048v vsen6 15 3vsb ain voltage sensing input. detect range is 0~2.048v vsen7 16 3vsb ain voltage sensing input. detect range is 0~2.048v vsen8 17 3vsb ain voltage sensing input. detect range is 0~2.048v 3vdd 18 - power +3v vdd power. it is also a voltage monitor channel. this pin has internal divided resistors to scale down the input voltage for analog voltage measurement. bypass with the parallel combination of 10 f (electrolytic or tantalum) and 0.1 f (ceramic) bypass capacitors. 3vsb 19 - power this pin is power for W83795ADG. it is also a voltage monitor channel. this pin has internal divided resistors to scale down the input voltage for analog voltage measurement. bypass with the parallel combination of 10 f (electrolytic or tantalum) and 0.1 f (ceramic) bypass capacitors. vbat 20 - power vbat supplies power for caseopen. besides, it is also a voltage monitor channel for +3v on-board battery. this pin has internal divided resistors to scale down the input
w83795g/adg - 24 ? aug/2/2010 revision 1.41 pin name pin no. power plane type description voltage for analog voltage measurement. caseopen# 21 vbat in ts caseopen detection. an active low input from an external device when chassis is intruded. this signal will be latched even the chassis is closed. vtt 22 vtt power intel? cpu vtt power. it is also a voltage monitor channel. detect range is 0~2.048v peci 23 3vsb v4 intel? cpu peci interface. (default) sysrstin# in ts system reset input. (default) when this pin is asserted to low, watch-dog timer will be reset. fanin13 in ts fan tachometer input prochot3# 24 3vsb v5 this is a bi-directional pin. as an input signal, when it is pulled to low, the corresponding fan control output pins will be set to a preset value. clkin 25 3vsb in ts system clock input. peci and fan functions will use this clock to drive logics. scl 26 3vsb in ts i 2 c serial bus clock. sda 27 3vsb in ts / od 12 i 2 c serial bus bi-directional data. smi# od 12 system management interrupt. (default) fanin14 in ts fan tachometer input prochot4# 28 3vsb v5 this is a bi-directional pin. as an input signal, when it is pull-ed to low, the corresponding fan control output pins will be set to a preset value. ovt# over temperature alert. low active. beep 29 3vsb od 12 beep output when abnormal event occurs. when this is no abnormal events, this pin asserts high. (default) pwrbtn# 30 3vsb od 12 power button output for enable/disable power supply. (default)
w83795g/adg - 25 ? aug/2/2010 revision 1.41 pin name pin no. power plane type description this pin is related to asf commands. prochot1# v5 this is a bi-directional pin. as an input signal, when it is pull-ed to low, the corresponding fan control output pins will be set to a preset value. wdtrst# od 12 output signal for system reset. (default) there are two reset sources: watch-dog timer and asf reset command. when reset event occurs, this pin will assert 100ms low pulse for system reset. prochot2# 31 3vsb v5 this is a bi-directional pin. as an input signal, when it is pull-ed to low, the corresponding fan control output pins will be set to a preset value. fanin1 32 3vsb in ts fan tachometer input fanctl1 out 12 / aout fan speed control pwm/dc output. when the power of 3vdd is 0v, this pin will drive logic 0. the power of this pin is supplied by 3vsb. it can be configured to pwm/dc mode by registers. default is pwm output. as dc output, 256 steps output voltage scaled to 0~3vsb. addr0 33 3vsb in ts i 2 c device address bit0 trapping during 3vsb power on. fanin2 34 3vsb in ts fan tachometer input fanctl2 35 3vsb out 12 / aout fan speed control pwm/dc output. when the power of 3vdd is 0v, this pin will drive logic 0. the power of this pin is supplied by 3vsb. it can be configured to pwm/dc mode by registers. default is dc output. as dc output, 256 steps output voltage scaled to 0~3vsb.
w83795g/adg - 26 ? aug/2/2010 revision 1.41 pin name pin no. power plane type description addr1 in ts i 2 c device address bit1 trapping during 3vsb power on. fanin3 36 3vsb in ts fan tachometer input fanin4 37 3vsb in ts fan tachometer input fanin5 38 3vsb in ts fan tachometer input fanin6 39 3vsb in ts fan tachometer input fanin7 40 3vsb in ts fan tachometer input fanin8 41 3vsb in ts fan tachometer input gnd 42 power system ground. gpio1 ints /od 12 general purpose i/o function. (default) fanin9 43 3vsb in ts fan tachometer input gpio2 ints /od 12 general purpose i/o function. (default) fanin10 44 3vsb in ts fan tachometer input gpio3 ints /od 12 general purpose i/o function. (default) fanin11 in ts fan tachometer input peci_req# 45 3vsb od 12 peci control signal for cpu entering c3/c4 state. gpio4 ints /od 12 general purpose i/o function. (default) fanin12 46 3vsb in ts fan tachometer input vref 47 3vsb aout reference voltage output. (2.048v)
w83795g/adg - 27 ? aug/2/2010 revision 1.41 pin name pin no. power plane type description tr5 thermistor 5 sensing input.(default) vsen12 48 3vsb ain voltage sensing input. detection range is 0~2.048v.
w83795g/adg - 28 ? aug/2/2010 revision 1.41 8. register summary ? bank0 nnemonic add (hex) por (hex) typ e description id, bank select registers bank select 00 80 rw bank select vender id fd 5c ro nuvoton vender id chip id fe 79 ro nuvoton chip id device id fb 5x ro nuvoton device id (x = 0,1,2?) configuration and address select registers i2caddr fc * ro i 2 c address config 01 1x rw configuration (64pin=11h,48pin=15h) multi-function pin control registers volt ctrl1/2 02/03 ff/38 rw voltage monitoring control registers temp ctrl1/2 04/05 1f/55 rw temperature monitoring control registers fanin ctrl1/2 06/07 ff/00 rw fanin monito ring control registers vmigb ctrl 08 0f rw voltage monitoring input gain buffer control gpio mode 09 00 rw gpio i/o mode control gpio in 0a * ro gpio input data gpio out 0b ff rw gpio output data watch dog timer registers wdt lock 0c 00 wo lock watch dog wdt enable 0d 00 rw watch dog enable wdt sts 0e 00 rw watch dog status wdt timer 0f 00 rw watch dog timeout timer voltage/temperature/fanin reading registers voltage/ temperature/ fanin reading 10-3b * ro monitored channel vsen1- vsen11, vtt, 3vdd, 3vsb, vbat, tr5/vsen12, tr6/vsen13, td1/tr1/vdsen14, td2/tr2/vdsen15, td3/tr3/vdsen16, td4/tr4/vdsen17, dts1-dts8, and fanin1-fanin8 readout high byte. vr lsb 3c * ro monitored channel readout low byte. smi# control and status registers smi ctrl 40 10 rw smi control smi sts 1 - smi sts 7 41-47 00 ro smi status register 1-7 smi mask 1 - 48-4e * rw smi mask register 1-7
w83795g/adg - 29 ? aug/2/2010 revision 1.41 nnemonic add (hex) por (hex) typ e description smi mask7 ovt and beep control registers beep ctrl1 - beep ctrl6 50-55 00 rw beep control register 1-6 ovt glb 58 00 rw ovt global enable ovt1 ctrl1 ovt1 ctrl2 59 5a 00 00 rw ovt1 control register 1-2 ovt2 ctrl1 ovt2 ctrl2 5b 5c 00 00 rw ovt2 control register 1-2 ovt2 ctrl1 ovt2 ctrl2 5d 5e 00 00 rw ovt3 control register 1-2 thermtrip and prochot control registers therm ctrl 5f 00 rw thermtrip control and status proc sts 60 00 rw prochot processor hot status proc1 ctrl proc4 ctrl 61 64 00 00 rw prochot1# - prochot4 processor hot control voltage fault control registers volt fault1- volt fault3 65-67 00 rw volt_fault# control register 1-3 fan fault control registers fan fault1 fan fault2 68 69 00 00 rw fan_fault# control register 1-2 vid control and status registers vid ctrl 6a 00 rw vid control dvid limhi/limlo 6b/6c 64/64 rw dynamic vid high / low tolerance vsen1-vsen3 vidin 6d-6f * ro vsen1-vsen3 vid input value voltage/temperature/fanin limitation registers vsen1_hl/ll~ vsen11_hl/ll 70-85 ff/00 rw vsen1 - vsen11 voltage high / low limit vtt_hl/ll 86/87 ff/00 rw vtt voltage high / low limit 3vdd_hl/ll 88/89 ff/00 rw 3vdd voltage high / low limit 3vsb_hl/ll 8a/8b ff/00 rw 3vsb voltage high / low limit vbat_hl/ll 8c/8d ff/00 rw vbat voltage high / low limit volt1_hl/ll_lsb 8e/8f ff/00 rw voltage high / low limit low byte register1 volt2_hl/ll_lsb 90/91 ff/00 rw voltage high / low limit low byte register2 volt3_hl/ll_lsb 92/93 3f/00 rw voltage high / low limit low byte register3
w83795g/adg - 30 ? aug/2/2010 revision 1.41 nnemonic add (hex) por (hex) typ e description volt4_hl/ll_lsb 94/95 ff/00 rw voltage high / low limit low byte register4 td1/tr1 critical/ critical hystersis 96/97 64/5f rw td1/tr1 critic al, critical hystersis td1/tr1 warning/ warning hystersis 98/99 55/50 rw td1/tr1 warn ing, warning hystersis td2/tr2 critical/ critical hystersis 9a/9b 64/5f rw td2/tr2 critical, critical hystersis td2/tr2 warning/ warning hystersis 9c/9d 55/50 rw td2/tr2 warning, warning hystersis td3/tr3 critical/ critical hystersis 9e/9f 64/5f rw td3/tr3 critical, critical hystersis td3/tr3 warning/ warning hystersis a0/a1 55/50 rw td3/tr3 warn ing, warning hystersis td4/tr4 critical/ critical hystersis a2/a3 64/5f rw td4/tr4 critical, critical hystersis td4/tr4 warning/ warning hystersis a4/a5 55/50 rw td4/tr4 warn ing, warning hystersis tr5 critical/ critical hystersis a6/a7 64/5f rw tr5 critical, critical hystersis tr5 warning/ warning hystersis a8/a9 55/50 rw tr5 warning, warning hystersis tr6 critical/ critical hystersis aa/ab 64/5f rw tr6 critical, critical hystersis tr6 warning/ warning hystersis ac/ad 55/50 rw tr6 warning, warning hystersis dts critical/ critical hystersis b2/b3 64/5f rw dts1-dts8 (digital temperature sensor) critical, critical hystersis dts warning/ warning hystersis b4/b5 55/50 rw dts1-dts8 (digital temperature sensor) warning, warning hystersis fanin1_hl - fanin14_hl b6-c3 ff rw fanin1-fanin14 fan tachometer high limit fhl1_lsb - fhl7_lsb c4-ca ee rw fanin1-fanin14 fan tachometer high limit low byte *: see registers description, 8.1 id, bank select registers inside the w83795g/adg resides three banks of regist ers. customers must se t the banks correctly to access correct registers. all the registers described here can be accessed in all banks.
w83795g/adg - 31 ? aug/2/2010 revision 1.41 8.1.1.1. bank select register (bank select) thre e banks of registers are inside the w83795g/adg. the register bank could be selected by programming the bank select register. all 00 hex addresses in these three banks are defined as bank select register. location: bank 0, 1, 2, 3 address 00 hex type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. default value: 80 hex bit description 7 hbacs (high byte access) 0 = return the low byte while reading nuvoton vendor id. 1 = return the high byte while reading nuvoton vendor id. 6-3 reserved. 2-0 bank select. 000 bin = bank 0 is selected. 001 bin = bank 1 is selected. 010 bin = bank 2 is selected. 011 bin = bank 3 is selected. 8.1.1.2. nuvoton vender id register (vender id) the nuvoton vender id contains two-by te data. by programming register hbacs , the customer can choose to access either the high or the low byte of nuvoton vender id. location: bank 0, 1, 2, 3 address fd hex type: read only reset: no reset default value: 5c hex / a3 hex bit description 7-0 vendor id. return 5c hex if hbacs = 1; return a3 hex if hbacs = 0. 8.1.1.3. nuvoton chip id register (chip id) location: bank 0, 1, 2, 3 address fe hex type: read only reset: no reset default value: 79 hex
w83795g/adg - 32 ? aug/2/2010 revision 1.41 bit description 7-0 chip id. chip id of w83795g/adg is 79 h ex 8.1.1.4. nuvoton device version id register (device id) location: bank 0, 1, 2, 3 address fb hex type: read only reset: no reset default value: 51 hex bit description 7-0 device id. device is w83795g/adg and 51 hex is for b version , 52 hex is for c version *a version chip device id is 50 hex in address ff hex. 8.2 configuration and address select registers 8.2.1.1. i 2 c address register (i2caddr) there are four addresses (58 hex , 5a hex , 5c hex , 5e hex ) that can be assigned for the i 2 c interface. these four addresses can be set by strapping addr0 & addr1 input value at 100ms after power ready. location: bank 0 address fc hex type: read only reset: 100ms after 3vsb rising. default value: na bit description 7 reserved. nuvoton test mode . test modes for production. nuvot on strongly suggests the customer not to use these registers to avoid system malfunction. 6-0 addr_hm. the value of addr_hm is w83795g/adg smbus slave address that strapped from addr0 and addr1 at 100ms after 3vsb power ready. addr1 addr0 i 2 c address 0 0 58 hex 0 1 5a hex
w83795g/adg - 33 ? aug/2/2010 revision 1.41 1 0 5c hex 1 1 5e hex 8.2.1.2. configuration register (config) config uration register controls the system reset source, stop, power down and warning output mode. location: bank 0 address 01 hex type: read / write reset: bit 0~1 & 3~4 & 7: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. bit 5 & 6: 3vsb rising, default value: 11 hex is for w83795g 15 hex is for W83795ADG bit description 7 init. setting to one restores power-on default values to all registers, except the serial bus address register. this bit clears itse lf since the power-on default is zero. 6 sysrst_md. 0 = no operation when the sysrstin # input signal is issued. 1 = the whole chip will be reset when the sysrstin# input signal is issued. 5 rst_vdd_md. 0 = no operation when 3vdd is up. 1 = the whole chip will be reset when 3vdd is up. 4-3 clksel. select clkin clock input. 00 bin = clkin clock input is 14.318mhz. 01 bin = clkin clock input is 24mhz. 10 bin = clkin clock input is 33mhz. (default) 11 bin = clkin clock input is 48mhz. 2 config48. package version (power on trapping), 0 = 64 pin package for w83795g 1 = 48 pin package for W83795ADG 1 int_clear. a one disables the smi# outputs without a ffecting the contents of interrupt status registers. the device will stop monitoring at last channel. it will resume upon clearing of this bit. 0 start.
w83795g/adg - 34 ? aug/2/2010 revision 1.41 bit description 0 = disable monitoring operations. 1 = enable monitoring operations. 8.3 multi-function pin control registers many functions exhibited in the w83795g/adg are not default functions, and might share pin out with other functions. here lists three registers that define the function enable registers. 8.3.1.1. monitoring control register setting to one will enabl e the corresponding monitoring channels. clearing to 0 will disable that monitoring channels. location:
w83795g/adg - 35 ? aug/2/2010 revision 1.41 volt ctrl1 - bank 0 address 02 hex volt ctrl2 - bank 0 address 03 hex temp ctrl1 - bank 0 address 04 hex temp ctrl2 - bank 0 address 05 hex fanin ctrl1 - bank 0 address 06 hex fanin ctrl2 - bank 0 address 07 hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. volt ctrl1 ? voltage monitoring control register location: bank 0 address 02 hex default value: ff hex bit description 7 en_vsen8 ? enable vsen8 voltage monitoring. 0 = disable 1 = enable 6 en_vsen7 ? enable vsen7 voltage monitoring. 0 = disable 1 = enable 5 en_vsen6 ? enable vsen6 voltage monitoring. 0 = disable 1 = enable 4 en_vsen5 ? enable vsen5 voltage monitoring. 0 = disable 1 = enable 3 en_vsen4 ? enable vsen4 voltage monitoring. 0 = disable 1 = enable 2 en_vsen3 ? enable vsen3 voltage monitoring. 0 = disable 1 = enable 1 en_vsen2 ? enable vsen2 voltage monitoring. 0 = disable 1 = enable 0 en_vsen1 ? enable vsen1 voltage monitoring. 0 = disable 1 = enable volt ctrl2 ? voltage monitoring control register location: bank 0 address 03 hex
w83795g/adg - 36 ? aug/2/2010 revision 1.41 default value: 38 hex bit description 7 reserved 6 en_vbat ? enable vbat voltage monitoring. 0 = disable (default) 1 = enable 5 en_3vsb ? enable 3vsb voltage monitoring. 0 = disable 1 = enable 4 en_3vdd ? enable 3vdd voltage monitoring. 0 = disable 1 = enable 3 en_vtt ? enable vtt voltage monitoring. 0 = disable 1 = enable 2 en_vsen11 ? enable vsen11 voltage monitoring. 0 = disable (default) 1 = enable (this function is not for W83795ADG) 1 en_vsen10 ? enable vsen10 voltage monitoring. 0 = disable (default) 1 = enable (this function is not for W83795ADG) 0 en_vsen9 ? enable vsen9 voltage monitoring. 0 = disable (default) 1 = enable (this function is not for W83795ADG) temp ctrl1 ? temperature monitoring control register location: bank 0 address 04 hex default value: 1f hex bit description 7 reserved 6 reserved 5 en_dts ? enable dts (digital temperature sensor) interface from intel peci or amd sb-tsi. 0 = disable (default) 1 = enable. note: program all registers about dts in bank 3 before enabling dts. 4 reserved 3-2 tr6/vsen13_md ? tr6/vsen13 monitoring selection mode. 0x bin = disable tr6/vsen13 monitoring 10 bin = enable vsen13 voltage monitoring
w83795g/adg - 37 ? aug/2/2010 revision 1.41 bit description 11 bin = enable tr6 thermistor temperature monitoring (default) 1-0 tr5/vsen12_md ? tr5/vsen12 monitoring selection mode. 0x bin = disable tr5/vsen12 monitoring 10 bin = enable vsen12 voltage monitoring 11 bin = enable tr5 thermistor temperature monitoring (default) temp ctrl2 ? temperature monitoring control register location: bank 0 address 05 hex default value: 55 hex bit description 7-6 td4/tr4/vdsen17_md ? td4/tr4/vdsen17 monitoring selection mode. note that it needs refer the application to set register. 00 bin = disable td4/tr4/vdsen17 monitoring 01 bin = enable td4 thermal diode temperature monitoring (default) 10 bin = enable vdsen17 different mode voltage monitoring 11 bin = enable tr4 thermistor temperature monitoring 5-4 td3/tr3/vdsen16_md ? td3/tr3/vdsen16 monitoring selection mode. note that it needs refer the application to set register. 00 bin = disable td3/tr3/vdsen16 monitoring 01 bin = enable td3 thermal diode temperature monitoring (default) 10 bin = enable vdsen16 different mode voltage monitoring 11 bin = enable tr3 thermistor temperature monitoring 3-2 td2/tr2/vdsen15_md ? td2/tr2/vdsen15 monitoring selection mode. note that it needs refer the application to set register. 00 bin = disable td2/tr2/vdsen15 monitoring 01 bin = enable td2 thermal diode temperature monitoring (default) 10 bin = enable vdsen15 different mode voltage monitoring 11 bin = enable tr2 thermistor temperature monitoring 1-0 td1/tr/vdsen14_md ? td1/tr1/vdsen14 monitoring selection mode. note that it needs refer the application to set register. 00 bin = disable td1/tr1/vdsen14 monitoring 01 bin = enable td1 thermal diode temperature monitoring (default) 10 bin = enable vdsen14 different mode voltage monitoring 11 bin = enable tr1 thermistor temperature monitoring fanin ctrl1 ? fanin monitoring control register location: bank 0 address 06 hex default value: ff hex bit description 7 en_fanin8 ? enable fanin8 monitoring.
w83795g/adg - 38 ? aug/2/2010 revision 1.41 0 = disable 1 = enable 6 en_fanin7 ? enable fanin7 monitoring. 0 = disable 1 = enable 5 en_fanin6 ? enable fanin6 monitoring. 0 = disable 1 = enable 4 en_fanin5 ? enable fanin5 monitoring. 0 = disable 1 = enable 3 en_fanin4 ? enable fanin4 monitoring. 0 = disable 1 = enable 2 en_fanin3 ? enable fanin3 monitoring. 0 = disable 1 = enable 1 en_fanin2 ? enable fanin2 monitoring. 0 = disable 1 = enable 0 en_fanin1 ? enable fanin1 monitoring. 0 = disable 1 = enable fanin ctrl2 ? fanin monitoring control register location: bank 0 address 07 hex default value: 00 hex bit description 7 -6 reserved 5 en_fanin14 ? select and enable smi#/fanin14/prochot4# multi-function pin. 0 = disable fanin14 monitoring. then sm i# and prochot4# can be selected by en_prochot4. 1 = enable fanin14 monitoring. 4 en_fanin13 ? select and enable sysrstin#/fanin 13/prochot3# multi-function pin. 0 = disable fanin13 monitoring. then sysr stin# and prochot3# can be selected by en_prochot3. 1 = enable fanin13 monitoring. 3 en_fanin12 ? select and enable fanin12/pvid3/gpio4 multi-function pin. 0 = disable fanin12 monitoring. then pvid3 and gpio4 can be selected by vid_tab. 1 = enable fanin12 monitoring. pvid3 function is not for W83795ADG. 2 en_fanin11 ? select and enable fanin11/peci_re q#/pvid2/gpio3 multi-function
w83795g/adg - 39 ? aug/2/2010 revision 1.41 bit description pin. 0 = disable fanin11 monitoring. then peci_ req#, pvid2 and gpio3 can be selected by vid_tab and en_voltfault. 1 = enable fanin11 monitoring. pvid2 function is not for W83795ADG. 1 en_fanin10 ? select and enable fanin10/pvid1/gpio2 multi-function pin. 0 = disable fanin10 monitoring. then pvid1 and gpio2 can be selected by vid_tab. 1 = enable fanin10 monitoring. pvid1 function is not for W83795ADG. 0 en_fanin9 ? select and enable fanin9/pvid0/gpio1 multi-function pin. 0 = disable fanin9 monitoring. then pvid0 and gpio1 can be selected by vid_tab. 1 = enable fanin9 monitoring. pvid0 function is not for W83795ADG. 8.3.1.2. voltage monitoring input gain buffer control register (vmigb ctrl) clea r to 0 will enable x8 input gain buffer for the corresponding voltage monitoring channels. set to 1 will enable x1 input gain buffer for the corresponding voltage monitoring channels. location: bank 0 address 08 hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. default value: 0f hex bit description 7-4 reserved 3 gain_vdsen17 ? enable vdsen17 voltage monitoring input gain buffer. 0 = x8 1 = x1 2 gain_vdsen16 ? enable vdsen16 voltage monitoring input gain buffer. 0 = x8 1 = x1 1 gain_vdsen15 ? enable vdsen15 voltage monitoring input gain buffer. 0 = x8 1 = x1 0 gain_vdsen14 ? enable vdsen14 voltage monitoring input gain buffer. 0 = x8 1 = x1
w83795g/adg - 40 ? aug/2/2010 revision 1.41 8.3.1.3. gpio control register (gpio ctrl) res et: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. gpio mode ? gpio i/o mode control register location: bank 0 address 09 hex default value: 00 hex type: read / write bit description 7-0 gpio mode ? select gpio8-gpio1 i/o mode. 0 = gpio8-1 are programming as input pins. (default) 1 = gpio8-1 are programming as output pins. bit7 is for gpio8 and bit6 is for gpio7, etc? bit[7:4] are reserved functions for W83795ADG. gpio in ? gpio input data register location: bank 0 address 0a hex default value: n.a. type: read only bit description 7-0 gpio in ? input gpio8-gpio1 data. the respective bits can be read only from pins. write accesses will be ignored. bit7 is for gpio8 and bit6 is for gpio7, etc? bit[7:4] are reserved functions for W83795ADG. gpio out ? gpio output data register location: bank 0 address 0b hex default value: ff hex type: read / write bit description 7-0 gpio out ? output gpio8-gpio1 data. for output ports, it needs to set gpio_mod register and the respective bits can be read/written and produced to pins. bit7 is for gpio8 and bit6 is for gpio7, etc? bit[7:4] are reserved functions for W83795ADG. 8.4 watch dog timer registers the w83795g/adg is integrated with a watch dog ti mer, which enables users to reset the system by wdtrst# (pin 39) while the system is in an abnor mal state. once watch dog timer is enabled, the
w83795g/adg - 41 ? aug/2/2010 revision 1.41 w83795g/adg starts to count down, and the host should set the timer for further count down or clear/disable the timer to prevent the w 83795g/adg from issuing reset signals. watch dog timer consists of four registers. wdt lock (bank0, cr0c) and wdt enable (bank0, cr0d) are used to activate soft-wdt and hard-wd t, respectively. wdt sts (bank0, cr0e) and wdt timer (bank0, cr0f) can inform the host whether the system time is up or not. two kinds of watchdog timer functions are suppor ted by the w83795g/adg. one is so-called soft watch dog timer, and the other is hard watch dog timer. hard watch dog timer, if enabled, will start a 4-minu te wdt after the system reset is completed. (a low-to-high transition on sysrstin# pin). bios needs to write a 00 hex into wdt timer (bank0, cr0f) to disable the timer within 4 minutes. otherwise, wdtrst# will assert to reset the system. soft watch dog timer will start counting down wh enever timeout time is set and soft watch dog timer is enabled. wdtrst# will be issued when the time runs out. soft watch dog timer will be disabled automatically after receiving sysrstin # low signal. wdt enable (bank0, cr0d [2]/ enwdt ) must be set to 1 if wish to program the four watch dog timer registers.
w83795g/adg - 42 ? aug/2/2010 revision 1.41 8.4.1 watch dog timer register details 8.4.1.1. lock watch dog register (wdt lock) writing this registe r enables the soft or hard watc h dog timer. this register type is write-only and wdt enable confirms whether the write is successful. location: bank 0 address 0c hex type: write only reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. default value: 00 hex bit description 7-0 unlock code write 55 hex , enables soft watch dog timer. write aa hex , disables soft watch dog timer. write 33 hex , enables hard watch dog timer. write cc hex , disables hard watch dog timer. 8.4.1.2. watch dog enable register (wdt enable) location: bank 0 address 0d hex type: read/write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. default value: 00 hex bit description 7-3 reserved. 2 enwdt. setting this bit to 1 will enable the watch dog timer function, which wdtrst# resets the system while the time is out. 1 hard. 0 = hard watch dog is disabled. 1 = hard watch dog is enabled. 0 soft. 0 = soft watch dog is disabled. 1 = soft watch dog is enabled. 8.4.1.3. watch dog status register (wdt sts)
w83795g/adg - 43 ? aug/2/2010 revision 1.41 location: bank 0 address 0e hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. default value: 00 hex bit description 7-4 reserved. 3-2 wdt_st. these 2 bits record last wdt stage for bios readout. the information is used to help bios to identify wdt timeout issuance. 1 hard_to. 1 = a hard timeout occurs. this bit will be cleared after reading. 0 soft_to. 1 = a soft timeout occurs. this bit will be cleared after reading. 8.4.1.4. watch dog timer register (wdt timer) location: ban k 0 address 0f hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. default value: 00 hex bit description 7-0 wdt timer ? timeout timer to write 00 hex can disable the timer while in hard watch dog timer mode. to set timeout time for soft watch dog timer, the unit is minute. timeout time is unit in minutes. 0 represents time is up or the timer is cleared. 1 represents there is still 1 minute time for this timer. similarly, 2 means there is still 2 minutes left. the second time will automatically be reset to 0 second when ti meout time register is set. 8.5 voltage/temperature/f anin re ading registers
w83795g/adg - 44 ? aug/2/2010 revision 1.41 8.5.1 voltage channel register details 8.5.1.1. voltage channel monitored value location: vsen1 - bank 0 address 10 hex vsen2 - bank 0 address 11 hex vsen3 - bank 0 address 12 hex vsen4 - bank 0 address 13 hex vsen5 - bank 0 address 14 hex vsen6 - bank 0 address 15 hex vsen7 - bank 0 address 16 hex vsen8 - bank 0 address 17 hex vsen9 - bank 0 address 18 hex vsen10 - bank 0 address 19 hex vsen11 - bank 0 address 1a hex vtt - bank 0 address 1b hex 3vdd - bank 0 address 1c hex 3vsb - bank 0 address 1d hex vbat - bank 0 address 1e hex vr lsb - bank 0 address 3c hex type: read only reset: 3vsb rising. voltage readout bit 7 6 5 4 3 2 1 0 name voltage readout value (high byte). 10-bit voltage value bit[9:2] ( vsen9-vsen11 bank0 address 18 hex -1a hex functions are not for W83795ADG) vr lsb bit 7 6 5 4 3 2 1 0 name voltage readout value (low byte). 10-bit voltage value bit[1:0] reserved voltage value calculation vr lsb together with voltage readout form s the 10-bit count value. if voltage readout (temperature readout high byte) is read succe ssively, the w83795g/adg will latch the vr lsb (temperature readout low byte) for next read. then voltage readout high byte and low byte are combined to 10-bitvoltagevalue . for vsen1-vsen13 and vdsen14-vdsen 17 and vtt voltage monitoring, real voltage calculations should follow the formula: 002.0 10)( ?= lue bitcountva vvoltage and the rest voltage 3vsb, 3vdd and vbat voltage moni toring, real voltage calc ulations should follow the formula: 006.0 10)( ?= lue bitcountva vvoltage 8.5.1.2. temperature/voltage channel monitored value
w83795g/adg - 45 ? aug/2/2010 revision 1.41 w83795g/adg have multi-function pins for temp erature and voltage monitoring. it needs set temp crl1 and temp crl2 registers to select temperature or voltage monitoring. if select temperature monitoring, the effective widt h of temperature readout value (high byte) and vr lsb (low byte) is for temperature data format is 10-bit 2?s complement (9-bit plus sign). location: tr5/vsen12 - bank 0 address 1f hex tr6/vsen13 - bank 0 address 20 hex td1/tr1/vdsen14 - bank 0 address 21 hex td2/tr2/vdsen15 - bank 0 address 22 hex td3/tr3/vdsen16 - bank 0 address 23 hex td4/tr4/vdsen17 - bank 0 address 24 hex vr lsb - bank 0 address 3c hex type: read only reset: 3vsb rising. for temperature monitoring selection: temperature readout bit 7 6 5 4 3 2 1 0 name temperature readout value (high byte). t he real temperature value calculation is referred to temperautre value caclulation description. 10-bit 2?s complement bit[9:2] value sign 64 32 16 8 4 2 1 vr lsb bit 7 6 5 4 3 2 1 0 name temperature readout value (low byte). 10-bit 2?s complement bit[1:0] reserved value 0.5 0.25 0 for voltage monitoring selection: voltage readout bit 7 6 5 4 3 2 1 0 name voltage readout value (high byte). the real voltage value calculation is referred to voltage value caclulation description. 10-bit voltage value bit[9:2] vr lsb bit 7 6 5 4 3 2 1 0 name voltage readout value (low byte). 10-bit voltage value bit[1:0] reserved
w83795g/adg - 46 ? aug/2/2010 revision 1.41 8.5.1.3. temperature channel monitored value before w83 795g/adg reads the dts1-dts8 (digital temperature sensor) temperature from intel peci or amd sb-tsi, it needs initial relative regist ers in bank3. the effective width of temperature readout value (high byte) and vr lsb (low byte) is for temperature data format is 10-bit 2?s complement (9-bit plus sign). location:
w83795g/adg - 47 ? aug/2/2010 revision 1.41 dts1 - bank 0 address 26 hex dts2 - bank 0 address 27 hex dts3 - bank 0 address 28 hex dts4 - bank 0 address 29 hex dts5 - bank 0 address 2a hex dts6 - bank 0 address 2b hex dts7 - bank 0 address 2c hex dts8 - bank 0 address 2d hex vr lsb - bank 0 address 3c hex type: read only reset: 3vsb rising. temperature readout bit 7 6 5 4 3 2 1 0 name temperature readout value (high byte). 10-bit 2?s complement bit[9:2] value sign 64 32 16 8 4 2 1 vr lsb bit 7 6 5 4 3 2 1 0 name temperature readout value (low byte). 10-bit 2?s complement bit[1:0] reserved. value 0.5 0.25 0 temperautre value calculation vr lsb together with temper autre readout forms the 10-bit count value. if temperautre readout (temperature readout high byte) is read successively, the w83795g/adg will latch the vr lsb (temperature readout low byte) for next read. then temperature readout high byte and low byte are combined to 10bits. temperature readout is r epresented 10-bit 2?s complement (9-bit plus sign) data format. note that it means thermal diode open when temperature value is -128 . the following table shows some examples. temperature temperautre readout (high byte) vr lsb (low byte) d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 +127.75 0 1 1 1 1 1 1 1 1 1 x x x x x x 0.25 0 0 0 0 0 0 0 0 0 1 x x x x x x 0 0 0 0 0 0 0 0 0 0 0 x x x x x x -1.25 1 1 1 1 1 1 1 0 1 1 x x x x x x -25.75 1 1 1 0 0 1 1 0 0 1 x x x x x x -128 1 0 0 0 0 0 0 0 0 0 x x x x x x
w83795g/adg - 48 ? aug/2/2010 revision 1.41 8.5.2 fan register details 8.5.2.1. fan tachometer readout high/low byte register (fanin count) the fani n_count maintains current count value of corresponding fan inputs. when 3vsb is on, it is cleared (00 hex ). the effective width of fanin_count (hi gh byte) and vr lsb (low byte) is 12-bit. location: fanin1 count - bank 0 address 2e hex fanin2 count - bank 0 address 2f hex fanin3 count - bank 0 address 30 hex fanin4 count - bank 0 address 31 hex fanin5 count - bank 0 address 32 hex fanin6 count - bank 0 address 33 hex fanin7 count - bank 0 address 34 hex fanin8 count - bank 0 address 35 hex fanin9 count - bank 0 address 36 hex fanin10 count - bank 0 address 37 hex fanin11 count - bank 0 address 38 hex fanin12 count - bank 0 address 39 hex fanin13 count - bank 0 address 3a hex fanin14 count - bank 0 address 3b hex vr lsb - bank 0 address 3c hex type: read only reset: 3vsb rising. default value: 00 hex fanin1_count~fanin14_count bit 7 6 5 4 3 2 1 0 name fanin_count (fanin tachometer readout high byte). the real fanin rpm value calculation is referred to fanin count caclulation description. 12-bitcount value bit[11:4] vr lsb bit 7 6 5 4 3 2 1 0 name fanin_count (fanin tachometer readout low byte) 12-bitcount value bit [3:0] reserved. fanin count calculation
w83795g/adg - 49 ? aug/2/2010 revision 1.41 vr lsb together with fanin count is form the 12-bit count value. if fanin count (fanin tachometer readout high byte) is read successively , the w83795g/adg will latch the vr lsb (fanin tachometer readout low byte) for next read. then fa nin tachometer high byte and low byte are combined to 12-bitcountvalue . real rpm (rotate per minute) calculations should follow the formula: ) 4 () 12( 1035.1 )( 6 fanpoles lue bitcountva rpmspeedfan ? = in this formula, fanpoles stands for the number of ns pole pairs inside the fan. normally an n-s-n-s fan ( fanpoles = 4) generates 2 pulses after completing one rotation. the frequency range for the fan tachometer is below 4.5 khz (if fanpoles=4, it means 135krpm). it is almost impossible, but a fan working faster than th is will cause the malfunction of the w83795g/adg. 8.6 smi# control and status registers several mechanisms are provided to alarm the system when monitored channels are abnormal. in this paragraph, three kinds of control/st atus registers are introduced. ?real time status? shows the current status of each channel; ?channel mask? defines wh ich channel needs to issue warning when abnormal operation occurs, and when the warning should be i gnored due to floating or in other circumstances. the final one is ?interrupt status,? which gives t he host information of which channel is issuing alert, and the host can base on this channel and do proper process to ensure a reliable system.
w83795g/adg - 50 ? aug/2/2010 revision 1.41 8.6.1 smi control/status register map the interrupt mode for voltage and fanin is only two-time interrupt mode. for temperature, there are three modes to serve: <1> comparator mode, <2>one-time interrupt mode, and <3> two-time interrupt mode. 8.6.1.1. smi control register (smi ctrl) location: bank 0 address 40 hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. default value: 10 hex bit description 7 rtsacs. 0 = read interrupt status from cr41~cr47 . (default) 1 = read real-time status from cr41~cr47 . 6-5 reserved. 4 smi_md. 0 = smi# outputs low level signal and active high. 1 = smi# outputs 200 us low pulse signal. (default) 3-2 temp_smi_md. temperature smi mode select. 00 bin = comparator interrupt mode: (default) temperature sensors exceeding t o (critical temperature) limit causes an interrupt and this interrupt will be cleared by reading all the interrupt status. 01 bin = two time interrupt mode: temperature sensors are used in the interrupt mode with hysteresis. temperature exceeding t o (critical temperature) causes an inte rrupt. temperatures that fall below t hyst (critical temperature hysteresis) will also ca use an interrupt if the previous interrupt has been reset by reading all the interrupt stat us register. once the temperature exceeds t o (critical temperature), an interrupt will be issued and the bit will be reset before the temperature falls to t hyst (critical temperature hysteresis). 10 bin = one time interrupt mode: temperature sensors are used in the interrupt mode with hysteresis. temperature exceeding t o (critical temperature) causes an interrupt and then temperature going below t hyst (critical temperature hysteresis) will not cause an interrupt. once an interrupt event has occurred by exceeding t o (critical temperature), then going below t hyst (critical temperature hysteresis), and interr upt will not occur again until the temperature exceeding t o (critical temperature). 11 bin = two time non-related interrupt mode: temperature sensors are used in the interrupt mode with hysteresis. temperature exceeding t o , causes an interrupt and then temperature going below t hyst will also cause an interrupt. once an interrupt ev ent has occurred by exceeding t o , then reset, if the temperature remains above the t hyst . if this mode is selected, for all monitor ch annels (it is not necessary to read the status
w83795g/adg - 51 ? aug/2/2010 revision 1.41 bit description for generating the next irq/smi# pulse. t critical twarning smi# ** ** ** twarning -hysteresis tcrit -hysteresis ** two-time intrrupt mode ** : interrupt status is read note: it can be programmed to be as not necessary to read the status for generating the next smi# pulse by setting temp_smi_md = 2'b11. 1 en_smi. 0 = disable smi# signal output. (default) 1 = enable smi# signal output. 0 smi_pol. 0 = default polarity. 1 = polarity inverted. 8.6.1.2. smi status register (smi sts) status regi ster can be read by interrupt or real -time mode and the function selected by smi control register cr40.bit7. if status register is read by interrupt mode and smi control register cr40.bit7 is set as 0 (default). then a one represents corresponding channel have been exceed its limit. status registers will clear the interrupt flag. if status register is read by real-time mode and smi c ontrol register cr40.bit7 is set as 1. then status registers show whether the values of related channe ls exceed the limit or not at the polling moment. the returning of 1 indicates the limit of related channel defined in limit registers has been exceeded. location: smi sts1 - bank 0 address 41 hex smi sts2 - bank 0 address 42 hex smi sts3 - bank 0 address 43 hex smi sts4 - bank 0 address 44 hex smi sts5 - bank 0 address 45 hex smi sts6 - bank 0 address 46 hex smi sts7 - bank 0 address 47 hex
w83795g/adg - 52 ? aug/2/2010 revision 1.41 type: read only reset: 3vsb rising. smi sts1 bit 7 6 5 4 3 2 1 0 name vsen8 vsen7 vsen6 vsen5 vsen4 vsen3 vsen2 vsen1 default 0 0 0 0 0 0 0 0 smi sts2 bit 7 6 5 4 3 2 1 0 name reserved vbat 3vsb 3vdd vtt vsen11 vsen10 vsen9 default 0 0 0 0 0 0 0 0 (bit 2:0 vsen9-vsen11 are not for W83795ADG) smi sts3 bit 7 6 5 4 3 2 1 0 name reserved reserved td4/tr4 vdsen17 td3/tr3 vdsen16 td2/tr2 vdsen15 td1/tr1 vdsen14 tr6 vsen13 tr5 vsen12 default 0 0 0 0 0 0 0 0 smi sts4 bit 7 6 5 4 3 2 1 0 name dts8 dts7 dts6 dts5 dts4 dts3 dts2 dts1 default 0 0 0 0 0 0 0 0 smi sts5 bit 7 6 5 4 3 2 1 0 name fanin8 fanin7 fanin6 fanin5 fanin4 fanin3 fanin2 fanin1 default 0 0 0 0 0 0 0 0 smi sts6 bit 7 6 5 4 3 2 1 0 name reserved chassis fanin14 fanin13 fanin12 fanin11 fanin10 fanin9 default 0 0 0 0 0 0 0 0
w83795g/adg - 53 ? aug/2/2010 revision 1.41 smi sts7 bit 7 6 5 4 3 2 1 0 name reserved tart6 tart5 tart4 tart3 tart2 tart1 default 0 0 0 0 0 0 0 0 8.6.1.3. smi mask register (smi mask) setting to one will disabl e the corresponding interrupt so urces. clearing to 0 will enable that interrupt source. smi mask6 cr4d.bit7 is clr_chs (c lear chassis), writing this bit to one will clear the internal caseopen latch. after the latch is cleared, clr_chs will self-reset to 0. location: smi mask1 - bank 0 address 48 hex smi mask2 - bank 0 address 49 hex smi mask3 - bank 0 address 4a hex smi mask4 - bank 0 address 4b hex smi mask5 - bank 0 address 4c hex smi mask6 - bank 0 address 4d hex smi mask7 - bank 0 address 4e hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. smi mask1 bit 7 6 5 4 3 2 1 0 name vsen8 vsen7 vsen6 vsen5 vsen4 vsen3 vsen2 vsen1 default 0 0 0 0 0 0 0 0 smi mask2 bit 7 6 5 4 3 2 1 0 name reserved vbat 3vsb 3vdd vtt vsen11 vsen10 vsen9 default 0 1 0 0 0 0 0 0 (bit 2:0 vsen9-vsen11 are not for W83795ADG) smi mask3
w83795g/adg - 54 ? aug/2/2010 revision 1.41 bit 7 6 5 4 3 2 1 0 name reserved reserved td4/tr4 vdsen17 td3/tr3 vdsen16 td2/tr2 vdsen15 td1/tr1 vdsen14 tr6 vsen13 tr5 vsen12 default 0 0 0 0 0 0 0 0 smi mask4 bit 7 6 5 4 3 2 1 0 name dts8 dts7 dts6 dts5 dts4 dts3 dts2 dts1 default 1 1 1 1 1 1 1 1 smi mask5 bit 7 6 5 4 3 2 1 0 name fanin8 fanin7 fanin6 fanin5 fanin4 fanin3 fanin2 fanin1 default 0 0 0 0 0 0 0 0 smi mask6 bit 7 6 5 4 3 2 1 0 name clr_chs chassis fanin14 fanin13 fanin12 fanin11 fanin10 fanin9 default 0 1 1 1 1 1 1 1 (the clr_chs must write 1 to clear inter nal caseopen latch status when vbat input.) smi mask7 bit 7 6 5 4 3 2 1 0 name reserved tart6 tart5 tart4 tart3 tart2 tart1 default 0 0 1 1 1 1 1 1 8.7 ovt and beep control registers another solution to deal with abnormal situation is through ovt (over temperature) or beep. ovt, as the name suggests, represents abnormal temper atures. in some applications, it can work with fan control to throttle the fan speed. beep can directly use sound of two tones to inform the user of abnormal system operation. unlike ovt, beep can be issued due to abnormal operations of any channel.
w83795g/adg - 55 ? aug/2/2010 revision 1.41 8.7.1 beep/ovt control registers details 8.7.1.1. beep control register (beep ctrl) setting to one will enable the corr esponding beep output. cleari ng to 0 will disable that beep output. the beep alarm function is enabled or disabled by the en_beep control bit at cr55.bit7. location: beep ctrl1 - bank 0 address 50 hex beep ctrl2 - bank 0 address 51 hex beep ctrl3 - bank 0 address 52 hex beep ctrl4 - bank 0 address 53 hex beep ctrl5 - bank 0 address 54 hex beep ctrl6 - bank 0 address 55 hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. beep ctrl1 bit 7 6 5 4 3 2 1 0 name vsen8 vsen7 vsen6 vsen5 vsen4 vsen3 vsen2 vsen1 default 0 0 0 0 0 0 0 0 beep ctrl2 bit 7 6 5 4 3 2 1 0 name reserved vbat 3vsb 3vdd vtt vsen11 vsen10 vsen9 default 0 0 0 0 0 0 0 0 (bit 2:0 vsen9-vsen11 are not for W83795ADG) beep ctrl3 bit 7 6 5 4 3 2 1 0 name reserved reserved td4/tr4 vdsen17 td3/tr3 vdsen16 td2/tr2 vdsen15 td1/tr1 vdsen14 tr6 vsen13 tr5 vsen12 default 0 0 0 0 0 0 0 0
w83795g/adg - 56 ? aug/2/2010 revision 1.41 beep ctrl4 bit 7 6 5 4 3 2 1 0 name dts8 dts7 dts6 dts5 dts4 dts3 dts2 dts1 default 0 0 0 0 0 0 0 0 beep ctrl5 bit 7 6 5 4 3 2 1 0 name fanin8 fanin7 fanin6 fanin5 fanin4 fanin3 fanin2 fanin1 default 0 0 0 0 0 0 0 0 beep ctrl6 bit 7 6 5 4 3 2 1 0 name en_beep chassis fanin14 fanin13 fanin12 fanin11 fanin10 fanin9 default 0 0 0 0 0 0 0 0 the beep alarm function is enabled or disabled by the en_beep control bit at cr55.bit7. if en_beep is set to 0, it is disabled beep output. (default) if en_beep is set to 1, it is enabled beep output. 8.7.1.2. ovt global enable register (ovt glb) location: bank 0 address 58 hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. default value: 00 hex bit description 7 ovt_sel. function select of beep for W83795ADG 1 = ovt# 0 = beep (default) 6 ovt_pol. 0 = ovt1#, ovt2# and ovt3# polarity is active low. (default) 1 = ovt1#, ovt2# and ovt3# polarity is active high. (ovt2# and ovt3# are not for W83795ADG) 5-4 reserved. 3 ovt_md.
w83795g/adg - 57 ? aug/2/2010 revision 1.41 bit description there are two ovt# signal output types. 0 bin : comparator mode: (default) temperature exceeding tcritical (critical temperature) activates the ovt# output until the temperature is lower than t hyst (critical temperature hysteresis). 1 bin : interrupt mode: temperatures exceeding tcritical (critica l temperature) will activate the ovt# output until temperature sensor s registers are read. if the current temperature rises from t hyst (critical temperature hysteresis) and exceeds tcritical (critical temperature), the ovt# pin will be de-asserted. if the temperature falls below t hyst , the ovt# pin will also generates an interrupt until it is reset by reading temperature sensors (interrupt stat us). once the interrupt is generated, the ovt# pin does not issue additional interrupts even it the temperature remains above tcritical. 2 en_ovt3. 0 = disable ovt3# output 1 = enable ovt3# output (ovt3# is not for W83795ADG) 1 en_ovt2. 0 = disable ovt2# output 1 = enable ovt2# output (ovt2# is not for W83795ADG) 0 en_ovt1. 0 = disable ovt1# output 1 = enable ovt1# output 8.7.1.3. ovt1 control register (ovt1 ctrl) setting to one will ena ble the corresponding ovt1# outpu t. clearing to 0 will disable that ovt1# output. the ovt1# function is enabled or disabled by the en_ovt1 control bit at cr58.bit0. the ovt1# signal will be issued when the selected temperature channel detects the temperature exceeds the allowed range 4 times in a row. location: ovt1 ctrl1 - bank 0 address 59 hex ovt1 ctrl2 - bank 0 address 5a hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set.
w83795g/adg - 58 ? aug/2/2010 revision 1.41 ovt1 crl1 bit 7 6 5 4 3 2 1 0 name reserved reserved td4/tr4 td3/tr3 td2/tr2 td1/tr1 tr6 tr5 default 0 0 0 0 0 0 0 0 ovt1 crl2 bit 7 6 5 4 3 2 1 0 name dts8 dts7 dts6 dts5 dts4 dts3 dts2 dts1 default 0 0 0 0 0 0 0 0 8.7.1.4. ovt2 control register (ovt2 ctrl) setting to one will ena ble the corresponding ovt2# outpu t. clearing to 0 will disable that ovt2# output. the ovt2# function is enabled or disabled by the en_ovt2 control bit at cr58.bit1. ovt2# is not for W83795ADG, it is reserved register. location: ovt2 ctrl1 - bank 0 address 5b hex ovt2 ctrl2 - bank 0 address 5c hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. ovt2 ctrl1 bit 7 6 5 4 3 2 1 0 name reserved reserved td4/tr4 td3/tr 3 td2/tr2 td1/tr1 tr6 tr5 default 0 0 0 0 0 0 0 0 ovt2 ctrl2 bit 7 6 5 4 3 2 1 0 name dts8 dts7 dts6 dts5 dts4 dts3 dts2 dts1 default 0 0 0 0 0 0 0 0 8.7.1.5. ovt3 control register (ovt3 ctrl)
w83795g/adg - 59 ? aug/2/2010 revision 1.41 setting to one will enable the corresponding ovt3# output. clearing to 0 will disable that ovt3# output. the ovt3# function is enabled or disabled by the en_ovt3 control bit at cr58.bit2. ovt3# is not for W83795ADG, it is reserved register. location: ovt3 ctrl1 - bank 0 address 5d hex ovt3 ctrl2 - bank 0 address 5e hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. ovt3 ctrl1 bit 7 6 5 4 3 2 1 0 name reserved reserved td4/tr4 td3/tr3 td2/tr2 td1/tr1 tr6 tr5 default 0 0 0 0 0 0 0 0 ovt3 ctrl2 bit 7 6 5 4 3 2 1 0 name dts8 dts7 dts6 dts5 dts4 dts3 dts2 dts1 default 0 0 0 0 0 0 0 0 8.8 thermtrip and prochot control registers 8.8.1.1. thermtrip control and status register (therm ctrl) setting to one will enable t he corresponding thrmtrip # . clearing to 0 will disable that thrmtrip# . location: bank 0 address 5f hex default value: 00 hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. bit description
w83795g/adg - 60 ? aug/2/2010 revision 1.41 7-3 reserved. 2 clr_thrm ? clear the thermal trip status. if write 1, to clear thermal trip status. 1 en_thrm ? enable thermal trip event. 0 = disable 1 = enable 0 thrm_sts ? thermal trip event status. (read only) 1 = thermal trip event occurred. power by vbat 8.8.1.2. prochot control and status registers whe n prochot# is set to be output and the corresponding temperature channel detects a temperature higher than the critical temperat ure, the prochot# signal will be issued. when prochot# is set to be input, it will be auto mapping to the table as below: prochot channel prochot1# prochot2# prochot3# prochot4# corresponding dts channel dts1 dts5 dts2 dts6 dts3 dts7 dts4 dts8 in smart fan control mode, if the prochot# is asserted by cpu, the fan which maps to corresponding dts channel will be full speed. for the fan mapping, also refer to 10.1.2.2 temperature to fan mapping relationships register and 10.1. 2.3 temperature source selection register. proc sts ? prochot processor hot status register location: bank 0 address 60 hex default value: 00 hex type: bit 5 & 4: read / write bit 3~0: read only reset: bit 5 & 4: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. bit 3~0: 3vsb rising, bit description 7-6 reserved. 5 set_prochot2 ? set the prochot2# function. for w83795g 0 = pin 39 is prochot2# 1 = pin 55 is prochot2# for W83795ADG 0 = pin 31 is prochot2# 1 = disable 4 set_prochot1 ? set the prochot1# function.
w83795g/adg - 61 ? aug/2/2010 revision 1.41 bit description for w83795g 0 = pin 38 is prochot1# 1 = pin 53 is prochot1# for W83795ADG 0 = pin 30 is prochot1# 1 = disable 3 sts_prochot4 ? status of prochot4# . 1 = meet cpu prochot# active. 2 sts_prochot3 ? status of prochot3# . 1 = meet cpu prochot# active. 1 sts_prochot2 ? status of prochot2#. 1 = meet cpu prochot# active. 0 sts_prochot1 ? status of prochot1#. 1 = meet cpu prochot# active. proc1 ctrl ? prochot1# processor hot control register location: bank 0 address 61 hex default value: 00 hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. bit description 7 en_prochot1 ? enable prochot1# function. 0 = disable 1 = enable 6 prochot1_mod ? set the prochot1# mode. 0 = input mode 1 = output mode 5 en_ph1_td4 ? enable prochot1# for td4/tr4. 0 = disable 1 = enable 4 en_ph1_td3 ? enable prochot1# for td3/tr3. 0 = disable 1 = enable 3 en_ph1_td2 ? enable prochot1# for td2/tr2. 0 = disable 1 = enable 2 en_ph1_td1 ? enable prochot1# for td1/tr1. 0 = disable 1 = enable
w83795g/adg - 62 ? aug/2/2010 revision 1.41 bit description 1 en_ph1_tr2 ? enable prochot1# for tr6. 0 = disable 1 = enable 0 en_ph1_tr1 ? enable prochot1# for tr5. 0 = disable 1 = enable proc2 ctrl ? prochot2# processor hot control register location: bank 0 address 62 hex default value: 00 hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. bit description 7 en_prochot2 ? enable prochot2# function. 0 = disable 1 = enable 6 prochot2_mod ? set the prochot2# mode. 0 = input mode 1 = output mode 5 en_ph2_td4 ? enable prochot2# for td4/tr4. 0 = disable 1 = enable 4 en_ph2_td3 ? enable prochot2# for td3/tr3. 0 = disable 1 = enable 3 en_ph2_td2 ? enable prochot2# for td2/tr2. 0 = disable 1 = enable 2 en_ph2_td1 ? enable prochot2# for td1/tr1. 0 = disable 1 = enable 1 en_ph2_tr2 ? enable prochot2# for tr6. 0 = disable 1 = enable 0 en_ph2_tr1 ? enable prochot2# for tr5. 0 = disable 1 = enable proc3 ctrl ? prochot3# processor hot control register
w83795g/adg - 63 ? aug/2/2010 revision 1.41 location: bank 0 address 63 hex default value: 00 hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. bit description 7 en_prochot3 ? enable prochot3# function. 0 = disable 1 = enable 6 prochot3_mod ? set the prochot3# mode. 0 = input mode 1 = output mode 5 en_ph3_td4 ? enable prochot3# for td4/tr4. 0 = disable 1 = enable 4 en_ph3_td3 ? enable prochot3# for td3/tr3. 0 = disable 1 = enable 3 en_ph3_td2 ? enable prochot3# for td2/tr2. 0 = disable 1 = enable 2 en_ph3_td1 ? enable prochot3# for td1/tr1. 0 = disable 1 = enable 1 en_ph3_tr2 ? enable prochot3# for tr6. 0 = disable 1 = enable 0 en_ph3_tr1 ? enable prochot3# for tr5. 0 = disable 1 = enable proc4 ctrl ? prochot4# processor hot control register location: bank 0 address 64 hex default value: 00 hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. bit description
w83795g/adg - 64 ? aug/2/2010 revision 1.41 bit description 7 en_prochot4 ? enable prochot4# function. 0 = disable 1 = enable 6 prochot4_mod ? set the prochot4# mode. 0 = input mode 1 = output mode 5 en_ph4_td4 ? enable prochot4# for td4/tr4. 0 = disable 1 = enable 4 en_ph4_td3 ? enable prochot4# for td3/tr3. 0 = disable 1 = enable 3 en_ph4_td2 ? enable prochot4# for td2/tr2. 0 = disable 1 = enable 2 en_ph4_td1 ? enable prochot4# for td1/tr1. 0 = disable 1 = enable 1 en_ph4_tr2 ? enable prochot4# for tr6. 0 = disable 1 = enable 0 en_ph4_tr1 ? enable prochot4# for tr5. 0 = disable 1 = enable 8.8.1.3. voltage fault control registers setting to on e will enable the corresponding volt_fault# output. clearing to 0 will disable that volt_fault# output. volt_fault# is not for W83795ADG , they are reserved registers. volt fault1 ? voltage fault control register 1 location: bank 0 address 65 hex default value: 00 hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. volt fault1 bit 7 6 5 4 3 2 1 0 name vsen8 vsen7 vsen6 vsen5 vsen4 vsen3 vsen2 vsen1 default 0 0 0 0 0 0 0 0
w83795g/adg - 65 ? aug/2/2010 revision 1.41 volt fault2 ? voltage fault control register 2 location: bank 0 address 66 hex default value: 00 hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. volt fault2 bit 7 6 5 4 3 2 1 0 name reserved vbat 3vsb 3vdd vtt vsen11 vsen10 vsen9 default 0 0 0 0 0 0 0 0 volt fault3 ? voltage fault control register 3 location: bank 0 address 67 hex default value: 00 hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. volt fault3 bit description 7 en_voltfault ? enable volt_fault# function. 0 = disable 1 = enable 6 reserved. 5-0 set_volt_cfg ? set the volt_fault# configuration. setting to one will enable the corresponding volt_fault# output. clearing to 0 will disable that volt_fault# output. bit5 is for vdsen17. bit4 is for vdsen16. bit3 is for vdsen15. bit2 is for vdsen14. bit1 is for vsen13. bit0 is for vsen12.
w83795g/adg - 66 ? aug/2/2010 revision 1.41 8.8.1.4. fan fault control registers setting to one will enabl e the corresponding fan_fault# output. clearing to 0 will disable that fan_fault# output. fan_fault# is not for W83795ADG , they are reserved registers. fan ctrl1 ? fan fault control register 1 location: bank 0 address 68 hex default value: 00 hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. fan fault1 bit 7 6 5 4 3 2 1 0 name fanin8 fanin7 fanin6 fanin5 fanin4 fanin3 fanin2 fanin1 default 0 0 0 0 0 0 0 0 fan ctrl2 ? fan fault control register 2 location: bank 0 address 69 hex default value: 00 hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. fan fault1 bit description 7 en_fanfault ? enable fan_fault# function. 0 = disable 1 = enable 6 reserved. 5-0 set_fan_cfg ? set the fan_fault# configuration. setting to one will enable the corresponding fan_fault# output. clearing to 0 will disable that fan_fault# output. bit5 is for fanin14. bit4 is for fanin13. bit3 is for fanin12. bit2 is for fanin11. bit1 is for fanin10. bit0 is for fanin9.
w83795g/adg - 67 ? aug/2/2010 revision 1.41 8.9 vid control and status registers the w83795g/adg provides vsen1, vsen2 and vsen 3 monitoring channels. vsen1, vsen2 and vsen3 channels are automatically monitored once 3vsb is applied onto the w83795g/adg, but the w83795g/adg will issue alert information only when the corres ponding high/low limits of vsen1, vsen2 and vsen3 channels are being violated. asf is also based on these limit registers to judge the current channel status and report to the host. two methods are used to assign the vsen1, vsen2 and vsen3 limits, manually or automatically by vid inputs. the following register sets allo w users to choose their preferred method. the w83795g/adg supplie s one set of vid input pins fo r vsen1, vsen2 and vsen3 channels. if dynamic vid function is enabled, the high/lo w limit of vsen1, vsen2 and vsen3 channel will auto-update when the vid input value changes. some vid input pins are multi-function pin. progr amming multi-function pin control registers properly is required to make these pins function. vid function is not for W83795ADG, they are reserved registers. 8.9.1.1. vid control register (vid ctrl) location: bank 0 address 6a hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. default value: 00 hex bit description 7 latch_vid. if write 1 (write clear), cr6d~cr6f latches the current pin value of vid. 6 vidl_acs. vid read out source cr6d~cr6f 0 = read vid input data 1 = read vid latch data 5 en_dvid3. if write 1, enable dynamic vid function for vsen3 if vid is changed, the high/low limit of corresponding vsen3 sensing voltage will be auto-updated. if manually programming high/low limit of vsen3 sensing voltage is required, this bit has to be cleared as 0. 4 en_dvid2. if write 1, enable dynamic vid function for vsen2 if vid is changed, the high/low limit of corresponding vsen2 sensing voltage will be auto-updated. if manually programming high/low limit of vsen2 sensing voltage is required, this bit has to be cleared as 0. 3 en_dvid1. if write 1, enable dynamic vid function for vsen1 if vid is changed, the high/low limit of corresponding vsen1 sensing voltage will be auto-updated. if manually programming high/low limit of vsen1 sensing voltage is required, this bit has to be cleared as 0.
w83795g/adg - 68 ? aug/2/2010 revision 1.41 bit description 2-0 vid_sel. vid function enable and vid table select: 000 bin = disable vid function and function of pin 57~64 are not about vid. (default) 001 bin = enable vrm9 table and pin 61~57 are vid[4:0]. 010 bin = enable vrm10 table and pin 63~57 are vid[6:0]. 011 bin = enable vrm11 table and pin 64~57 are vid[7:0]. 100 bin = enable amd opteron tm 5 bit vid codes and pin 61~57 are vid[4:0]. 101 bin = enable amd opteron tm 6 bit vid codes and pin 62~57 are vid[5:0]. 110 bin = enable amd svid table and pin 63~64 are scl_svi and sda_svi. 111 bin = disable vid function and function of pin 57~64 are not about vid. 8.9.1.2. dynamic vid high tolerance register (dvid limhi) location: bank 0 address 6b hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. default value: 64 hex bit description 7-0 dynamic vid high tolerance. if the dynamic vid function (set bank0 cr6a bit5-3 to 1) is enabled, writing tolerance register will force vsen1, vsen2 and vsen3 li mit to update with new voltage limits for vsen1, vsen2 and vsen3. the unit is 2mv 8.9.1.3. dynamic vid low tolerance register (dvid limlo) location: bank 0 address 6c hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. default value: 64 hex bit description 7-0 dynamic vid low tolerance. if the dynamic vid function (set bank0 cr6a bit5-3 to 1) is enabled, writing tolerance register will force vsen1, vsen2 and vsen3 li mit generator to generate new voltage limits for vsen1, vsen2 and vsen3. the unit is 2mv
w83795g/adg - 69 ? aug/2/2010 revision 1.41 8.9.1.4. vsen1 vid input value register (vsen1 vidin) location: bank 0 address 6d hex type: read only default value: na bit description 7-0 vidin_vsen1 the value of vidin_vsen1 is determin ed by setting vid control register cr6a . 8.9.1.5. vsen2 vid input value register (vsen2 vidin) location: bank 0 address 6e hex type: read only default value: na bit description 7-0 vidin_vsen2 the value of vidin_vsen2 is determin ed by setting vid control register cr6a . 8.9.1.6. vsen3 vid input value register (vsen3 vidin) location: bank 0 address 6f hex type: read only default value: na bit description 7-0 vidin_vsen3 the value of vidin_vsen3 is determin ed by setting vid control register cr6a . 8.10 voltage/temperature/fani n limitation reg isters vsen9-vsen11 functions are not for w83795a dg, they are reserved registers. 8.10.1.1. voltage channel limitation registers location: vsen1_hl - bank 0 address 70 hex vsen1_ll - bank 0 address 71 hex vsen2_hl - bank 0 address 72 hex vsen2_ll - bank 0 address 73 hex vsen3_hl - bank 0 address 74 hex vsen3_ll - bank 0 address 75 hex vsen4_hl - bank 0 address 76 hex vsen4_ll - bank 0 address 77 hex vsen5_hl - bank 0 address 78 hex vsen5_ll - bank 0 address 79 hex vsen6_hl - bank 0 address 7a hex vsen6_ll - bank 0 address 7b hex vsen7_hl - bank 0 address 7c hex
w83795g/adg - 70 ? aug/2/2010 revision 1.41 vsen7_ll - bank 0 address 7d hex vsen8_hl - bank 0 address 7e hex vsen8_ll - bank 0 address 7f hex vsen9_hl - bank 0 address 80 hex vsen9_ll - bank 0 address 81 hex vsen10_hl - bank 0 address 82 hex vsen10_ll - bank 0 address 83 hex vsen11_hl - bank 0 address 84 hex vsen11_ll - bank 0 address 85 hex vtt_hl - bank 0 address 86 hex vtt_ll - bank 0 address 87 hex 3vdd_hl - bank 0 address 88 hex 3vdd_ll - bank 0 address 89 hex 3vsb_hl - bank 0 address 8a hex 3vsb_ll - bank 0 address 8b hex vbat_hl - bank 0 address 8c hex vbat_ll - bank 0 address 8d hex volt1_hl_lsb - bank 0 address 8e hex volt1_ll_lsb - bank 0 address 8f hex volt2_hl_lsb - bank 0 address 90 hex volt2_ll_lsb - bank 0 address 91 hex volt3_hl_lsb - bank 0 address 92 hex volt3_ll_lsb - bank 0 address 93 hex volt4_hl_lsb - bank 0 address 94 hex volt4_ll_lsb - bank 0 address 95 hex reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. voltage hl/ll (high byte) bit 7 6 5 4 3 2 1 0 name vsen1_hl, vsen1_ll, vsen2_hl, vsen2_ll, vsen3_hl, vsen3_ll, vsen4_hl, vsen4_ll, vsen5_hl, vsen5_ll, vsen6_hl, vsen6_ll, vsen7_hl, vsen7_ll, vsen8_hl, vsen8_ll, vsen9_hl, vsen9_ll, vsen10_hl, vsen10_ll, vsen11_hl, vsen11_ll, vtt_hl, vtt_ll, 3vdd_hl, 3vdd_ll, 3vsb_hl, 3vsb_ll, vbat_hl, vbat_ll. voltage high / low limit (high byte). the real voltage value calculation is referred to voltage value caclulation description. 10-bit voltage value bit[9:2] high limit default value is ff hex low limit default value is 00 hex vsen9-vsen11 functions are not for w8379 5adg, they are reserved registers.
w83795g/adg - 71 ? aug/2/2010 revision 1.41 volt1_hl/ll_lsb (low byte) bit 7 6 5 4 3 2 1 0 vsen4_lsb vsen3_lsb vsen2_lsb vsen1_lsb name voltage high / low limit (low byte). 10-bit voltage value bit[1:0] volt1_hl_lsb default value is ff hex volt1_ll_lsb default value is 00 hex volt2_hl/ll_lsb (low byte) bit 7 6 5 4 3 2 1 0 vsen8_lsb vsen7_lsb vsen6_lsb vsen5_lsb name voltage high / low limit (low byte). 10-bit voltage value bit[1:0] volt2_hl_lsb default value is ff hex volt2_ll_lsb default value is 00 hex volt3_hl/ll_lsb (low byte) bit 7 6 5 4 3 2 1 0 reserved vsen11_lsb vsen10_lsb vsen9_lsb name voltage high / low limit (low byte). 10-bit voltage value bit[1:0] volt3_hl_lsb default value is 3f hex volt3_ll_lsb default value is 00 hex vsen9-vsen11 functions are not for w83795a dg, they are reserved registers. volt4_hl/ll_lsb (low byte) bit 7 6 5 4 3 2 1 0 vbat_lsb 3vsb_lsb 3vdd_lsb vtt_lsb name voltage high / low limit (low byte). 10-bit voltage value bit[1:0] volt4_hl_lsb default value is ff hex volt4_ll_lsb default value is 00 hex
w83795g/adg - 72 ? aug/2/2010 revision 1.41 8.10.1.2. temperature/voltage channel limitation registers w83 795g/adg have multi-function pins for temp erature and voltage monitoring. it needs set temp crl1 and temp crl2 registers to select temperature or voltage monitoring. if select temperature monitoring, the effective width of data format is 10-bit 2?s complement (9-bit plus sign). location: for select temperature monitoring: td1/tr1 critical - bank 0 address 96 hex td1/tr1 critical hystersis - bank 0 address 97 hex td1/tr1 warning - bank 0 address 98 hex td1/tr1 warning hystersis - bank 0 address 99 hex td2/tr2 critical - bank 0 address 9a hex td2/tr2 critical hystersis - bank 0 address 9b hex td2/tr2 warning - bank 0 address 9c hex td2/tr2 warning hystersis - bank 0 address 9d hex td3/tr3 critical - bank 0 address 9e hex td3/tr3 critical hystersis - bank 0 address 9f hex td3/tr3 warning - bank 0 address a0 hex td3/tr3 warning hystersis - bank 0 address a1 hex td4/tr4 critical - bank 0 address a2 hex td4/tr4 critical hystersis - bank 0 address a3 hex td4/tr4 warning - bank 0 address a4 hex td4/tr4 warning hystersis - bank 0 address a5 hex tr5 critical - bank 0 address a6 hex tr5 critical hystersis - bank 0 address a7 hex tr5 warning - bank 0 address a8 hex tr5 warning hystersis - bank 0 address a9 hex tr6 critical - bank 0 address aa hex tr6 critical hystersis - bank 0 address ab hex tr6 warning - bank 0 address ac hex tr6 warning hystersis - bank 0 address ad hex reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. critical temperature bit 7 6 5 4 3 2 1 0 name td1/tr1, td2/tr2, td3/tr3, td4/tr4, tr5, tr6 critical critical temperature value. the format of temperature is 8-bit 2?s complement and the range is ?128 ~127 . value sign 64 32 16 8 4 2 1 default 64 hex (100 )
w83795g/adg - 73 ? aug/2/2010 revision 1.41 critical temperature hystersis bit 7 6 5 4 3 2 1 0 name td1/tr1, td2/tr2, td3/tr3, td4/tr 4, tr5, tr6 critical hystersis critical temperature hysteresis value. the format of temperature is 8-bit 2?s complement and the range is ?128 ~127 . value sign 64 32 16 8 4 2 1 default 5f hex (95 ) warning temperature bit 7 6 5 4 3 2 1 0 name td1/tr1, td2/tr2, td3/tr3, td4/tr4, tr5, tr6 warning warning temperature value. the format of temperature is 8-bit 2?s complement and the range is ?128 ~127 . value sign 64 32 16 8 4 2 1 default 55 hex (85 ) warning temperature hystersis bit 7 6 5 4 3 2 1 0 name td1/tr1, td2/tr2, td3/tr3, td4/ tr4, tr5, tr6 warning hystersis warning temperature hysteresis value. the format of temperature is 8-bit 2?s complement and the range is ?128 ~127 . value sign 64 32 16 8 4 2 1 default 50 hex (80 ) for select voltage monitoring: vdsen14_hl - bank 0 address 96 hex vdsen14_ll - bank 0 address 97 hex vdsen14_hl_lsb - bank 0 address 98 hex vdsen14_ll_lsb - bank 0 address 99 hex vdsen15_hl - bank 0 address 9a hex vdsen15_ll - bank 0 address 9b hex vdsen15_hl_lsb - bank 0 address 9c hex vdsen15_ll_lsb - bank 0 address 9d hex vdsen16_hl - bank 0 address 9e hex vdsen16_ll - bank 0 address 9f hex vdsen16_hl_lsb - bank 0 address a0 hex vdsen16_ll_lsb - bank 0 address a1 hex
w83795g/adg - 74 ? aug/2/2010 revision 1.41 vdsen17_hl - bank 0 address a2 hex vdsen17_ll - bank 0 address a3 hex vdsen17_hl_lsb - bank 0 address a4 hex vdsen17_ll_lsb - bank 0 address a5 hex vsen12_hl - bank 0 address a6 hex vsen12_ll - bank 0 address a7 hex vsen12_hl_lsb - bank 0 address a8 hex vsen12_ll_lsb - bank 0 address a9 hex vsen13_hl - bank 0 address aa hex vsen13_ll - bank 0 address ab hex vsen13_hl_lsb - bank 0 address ac hex vsen13_ll_lsb - bank 0 address ad hex reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. vdsen_hl/ll (high byte) bit 7 6 5 4 3 2 1 0 name vdsen14_hl, vdsen14_ll, vdsen15_hl, vdsen15_ll, vdsen16_hl, vdsen16_ll, vdsen17_hl, vdsen17_ll vsen12_hl, vsen12_ll, vsen13_hl, vsen13_ll voltage high / low limit (high byte). the real voltage value calculation is referred to voltage value caclulation description. 10-bit voltage value bit[9:2] default vdsen_hl default value is 64 hex vdsen_ll default value is 5f hex vdsen_hl/ll_lsb (low byte) bit 7 6 5 4 3 2 1 0 vdsen_hl/ll_lsb unused. name vdsen14_hl_lsb, vdsen14_ll_lsb, vdsen15_hl_lsb, vdsen15_ll_lsb, vdsen16_hl_lsb, vdsen16_ll_lsb, vdsen17_hl_lsb, vdsen17_ll_lsb vsen12_hl_lsb, vsen12_ll_lsb, vsen13_hl_lsb, vsen13_ll voltage high / low limit (low byte). 10-bit voltage value bit[1:0] default vdsen_hl_lsb default value is 50 hex vdsen_ll_lsb default value is 64 hex
w83795g/adg - 75 ? aug/2/2010 revision 1.41 8.10.1.3. temperature channel limitation registers before w837 95g/adg reads dts1-dts8 (digital temperature sensor) temperature from intel peci or amd sb-tsi, it needs initial relative register s in bank3. the effective width of temperature readout value (high byte) and vr lsb (low byte) is for temperature data format is 10-bit 2?s complement (9-bit plus sign). location: dts critical - bank 0 address b2 hex dts critical hystersis - bank 0 address b3 hex dts warning - bank 0 address b4 hex dts warning hystersis - bank 0 address b5 hex reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. critical temperature bit 7 6 5 4 3 2 1 0 name dts critical critical temperature value. the format of temperature is 8-bit 2?s complement and the range is ?128 ~127 . value sign 64 32 16 8 4 2 1 default 64 hex (100 ) critical temperature hystersis bit 7 6 5 4 3 2 1 0 name dts critical hystersis critical temperature hysteresis value. the format of temperature is 8-bit 2?s complement and the range is ?128 ~127 . value sign 64 32 16 8 4 2 1 default 5f hex (95 ) warning temperature bit 7 6 5 4 3 2 1 0 name dts warning warning temperature value. the format of temperature is 8-bit 2?s complement and the range is ?128 ~127 . value sign 64 32 16 8 4 2 1
w83795g/adg - 76 ? aug/2/2010 revision 1.41 default 55 hex (85 ) warning temperature hystersis bit 7 6 5 4 3 2 1 0 name dts warning hysteresis warning temperature hysteresis value. the format of temperature is 8-bit 2?s complement and the range is ?128 ~127 . value sign 64 32 16 8 4 2 1 default 50 hex (80 ) 8.10.1.4. fanin count limitation registers the f anin_hl and fhl_lsb are combined to 12-bit fanin limit. it sets up the limit range for the fanin count values. if the counter counts value larger than what the registers indicate, the w83795g/adg will show alert in the real-time status and may take further actions based on user setups. location: fanin1_hl - bank 0 address b6 hex fanin2_hl - bank 0 address b7 hex fanin3_hl - bank 0 address b8 hex fanin4_hl - bank 0 address b9 hex fanin5_hl - bank 0 address ba hex fanin6_hl - bank 0 address bb hex fanin7_hl - bank 0 address bc hex fanin8_hl - bank 0 address bd hex fanin9_hl - bank 0 address be hex fanin10_hl - bank 0 address bf hex fanin11_hl - bank 0 address c0 hex fanin12_hl - bank 0 address c1 hex fanin13_hl - bank 0 address c2 hex fanin14_hl - bank 0 address c3 hex fhl1_lsb - bank 0 address c4 hex fhl2_lsb - bank 0 address c5 hex fhl3_lsb - bank 0 address c6 hex fhl4_lsb - bank 0 address c7 hex fhl5_lsb - bank 0 address c8 hex fhl6_lsb - bank 0 address c9 hex fhl7_lsb - bank 0 address ca hex reset: 3vsb rising. init reset (cr01.bit7) is set,
w83795g/adg - 77 ? aug/2/2010 revision 1.41 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. fanin1_hl ~ fanin14_hl bit 7 6 5 4 3 2 1 0 name fanin1_hl ~ fanin14_hl fanin tachometer count limit (high byte). the real fanin rpm count limit value calculation is referred to fanin count caclulation description. 12-bitcount value bit[11:4] default ff hex fhl1_lsb bit 7 6 5 4 3 2 1 0 fanin2_hl_lsb fanin1_hl_lsb name fanin1 and fanin2 tachometer count limit (lowe byte). 12-bitcount value bit [3:0] default ee hex fhl2_lsb bit 7 6 5 4 3 2 1 0 fanin4_hl_lsb fanin3_hl_lsb name fanin3 and fanin4 tachometer count limit (lowe byte). 12-bitcount value bit [3:0] default ee hex fhl3_lsb bit 7 6 5 4 3 2 1 0 fanin6_hl_lsb fanin5_hl_lsb name fanin5 and fanin6 tachometer count limit (lowe byte). 12-bitcount value bit [3:0] default ee hex fhl4_lsb bit 7 6 5 4 3 2 1 0
w83795g/adg - 78 ? aug/2/2010 revision 1.41 fanin8_hl_lsb fanin7_hl_lsb name fanin7 and fanin8 tachometer count limit (lowe byte). 12-bitcount value bit [3:0] default ee hex fhl5_lsb bit 7 6 5 4 3 2 1 0 fanin10_hl_lsb fanin9_hl_lsb name fanin9 and fanin10 tachometer count limit (lowe byte). 12-bitcount value bit [3:0] default ee hex fhl6_lsb bit 7 6 5 4 3 2 1 0 fanin12_hl_lsb fanin11_hl_lsb name fanin11 and fanin12 tachometer count limit (lowe byte). 12-bitcount value bit [3:0] default ee hex fhl7_lsb bit 7 6 5 4 3 2 1 0 fanin14_hl_lsb fanin13_hl_lsb name fanin13 and fanin14 tachometer count limit (lowe byte). 12-bitcount value bit [3:0] default ee hex 8.11 temperature sensors offset registers 8.11.1.1. temperature offset register
w83795g/adg - 79 ? aug/2/2010 revision 1.41 each temperature channel has a corresponding offset register. in some situations, the customer may want to shift the offset. the default is 00 hex . location: td1 offset - bank 0 address d0 hex td2 offset - bank 0 address d1 hex td3 offset - bank 0 address d2 hex td4 offset - bank 0 address d3 hex tr5/6 offset - bank 0 address d4 hex reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. td1-td4 offset temperature bit 7 6 5 4 3 2 1 0 name td1, td2, td3, td4 offset offset temperature value. the format of temperature is 6-bit 2?s complement and the range is ?32 ~31 . value reserved sign 16 8 4 2 1 default 00 hex (0 ) tr1/2 offset temperature bit 7 6 5 4 3 2 1 0 tr6 offset tr5 offset name offset temperature value. the format of temperature is 4-bit 2?s complement and the range is ?8 ~7 . value sign 4 2 1 sign 4 2 1 default 00 hex (0 )
w83795g/adg - 80 ? aug/2/2010 revision 1.41 9. register summary ? bank1 nnemonic add (hex) por (hex) type description udidddevcap 20 c1 ro udid device capability. udidversion 21 08 ro udid version number udidvendor 22/23 10/50 ro udid vendor id udiddev 24/25 79/5a rw udid device id udidif 26/27 00/24 rw udid interface udidsubven 28/29 00/00 rw udid subsystem vendor id udidsubdev 2a/2b 00/00 rw udid subsystem device id udidspecid 2c-2f * rw udid vendor-specific id rng 30-33 * ro random number generator asfadd 3f 00 ro asf assigned address enty 40-72 * rw asf entity entins 80-a3 * rw asf entity instance pwronoption b0 00 rw power on control option pwroncmd b1 11 rw power on command pwrdncmd b2 12 rw power down command rstcmd b3 10 rw remote reset command asftm b4 ff wo asf test mode *: see registers description 9.1 asf control registers asf or a lert s tandard f ormat provides remote system abilities to monitor, discover and manage the local platform. all asf control registers are located in bank 1*. *about the bank selection, please refer to the bank select register located at address 00 hex. 9.1.1.1. smbus arp udid control registers before a ctivating asf, the user must go through the arp (address resolution protocol) to dynamically obtain a valid address to manipulate asf commands. in arp, it is very important that udid (u nique d evice id entifier) is defined to distinguish different devices. registers in this section are used to set up udid. for detailed operation of arp and udid, please refer to smbus specification version 2.0 ( http://www.smbus.org/specs/smbus20.pdf ) section 5.6 in page 34.
w83795g/adg - 81 ? aug/2/2010 revision 1.41 9.1.1.2. asf sensor entity definition registers in asf sensor, each sensor channel has 2 paramete rs, entity instance and entity id, to tell the asf host its related location information on the platform. if the user uses the temperature sensor in locations different from the default, the w83795g/adg provid es all channel parameters that can be programmed to fit customers? application. for details of entity id, please refer to platform event trap f ormat specification version 1.0 table 6 in page 13. entity instance is a sequential number which helps i dentify the sensor?s location. the customer can set preferable sequence orders. the summary of entity and entity instance is in the following table. note that all channels can be disabled by multi- function pin selection or control registers. vsen9-vsen11 functions are not for w83795a dg, they are reserved registers. sensor in w83795g/adg event status index event sensor type event number entity id (programmable) entity instance (programmable) vsen1 00h 01h 01h vsen2 01h 02h 02h vtt 02h 02h (voltage) 03h 03h dts1 03h 04h 01h dts2 04h 05h 02h dts3 05h 06h 03h dts4 06h 07h 04h dts5 07h 08h 05h dts6 08h 09h 06h dts7 09h 0ah 07h dts8 0ah 01h (temperature) 0bh 03h (processor) 08h td1/tr1 0bh 0ch 01h td2/tr2 0ch 0dh 02h td3/tr3 0dh 0eh 03h td4/tr4 0eh 0fh 04h tr5 0fh 10h 05h tr6 10h 11h 06h reserved 11h 01h (temperature) 12h 07h 3vdd 12h 13h 01h 3vsb 13h 14h 02h vbat 14h 15h 03h vsen3 15h 16h 04h vsen4 16h 02h (voltage) 17h 07h (system board) 05h
w83795g/adg - 82 ? aug/2/2010 revision 1.41 sensor in w83795g/adg event status index event sensor type event number entity id (programmable) entity instance (programmable) vsen5 17h 18h 06h vsen6 18h 19h 07h vsen7 19h 1ah 08h vsen8 1ah 1bh 09h vsen9 1bh 1ch 0ah vsen10 1ch 1dh 0bh vsen11 1dh 1eh 0ch vsen12 1eh 1fh 0dh vsen13 1fh 20h 0eh vdsen14 20h 21h 0fh vdsen15 21h 22h 10h vdsen16 22h 23h 11h vdsen17 23h 24h 12h fanin1 24h 25h 01h fanin2 25h 26h 02h fanin3 26h 27h 03h fanin4 27h 28h 04h fanin5 28h 29h 05h fanin6 29h 2ah 06h fanin7 2ah 2bh 07h fanin8 2bh 2ch 08h fanin9 2ch 2dh 09h fanin10 2dh 2eh 0ah fanin11 2eh 2fh 0bh fanin12 2fh 30h 0ch fanin13 30h 31h 0dh fanin14 31h 04h (fan) 32h 0eh case open / intrusion 32h 05h (physical security) 33h 23h (system chassis) 01h
w83795g/adg - 83 ? aug/2/2010 revision 1.41 the channels in light-green can be disabled by mult i-function pin selection or control registers. the channels are described in the following terms according to the status of each channel. description status event sensor type event type event offset event severity temperature sensors upper-critical going high 09h upper-critical going low 08h 10h critical upper-non-critical going high 07h upper-non-critical going low 3h assert 06h 08h non-critical lower-non-critical going high 01h lower-non-critical going low 2h deassert 01h temperature 01h threshold- based 00h 01h monitor voltage sensors generic over voltage problem 3h 02h 10h normal voltage 2h 07h 01h generic under voltage problem 3h 02h voltage 07h generic- severity 02h 10h fan sensors normal fan speed 2h 07h 01h generic fan failure 3h 04h fan 07h 02h 10h caseopen/ case intrusion case intruded 3h 00h 10h case normal 2h 05h physical security 6fh sensor specific 80h 01h
w83795g/adg - 84 ? aug/2/2010 revision 1.41 9.1.1.3. asf remote control definition registers asf function in the w8379 5g/adg also supports re mote control. this function enables management information system (mis) to remotely power on, powe r down, or reset the client?s computer when there is abnormal operation. the remote control function in the w83795g/adg enables mis to use side-band of network interface controller to send asf commands with smbus. the format looks like 1 7 1 1 8 1 8 1 8 1 1 s slave address wr a command a write data a pec a p control device address 0 0 control command 0 control data value 0crc checksum 0 ?s? represents ?start? cycle of smbus transaction; ?wr? means ?write? flag; ?a? means ?acknowledge? from the w83795g/adg, and ?p? indicates a ?stop? cy cle. letters in shadow mean responses from the w83795g/adg. otherwise, it is a host transmitted signal. the last row above shows the meani ng of each data. control device address is the address assigned in the arp process; control command is specified in the above registers. control data option is not supported in the w83795g/adg. thus with any val ue in this field, the w83795g/adg will perform the same action. please refer to section 5.4 in page 76 and section 3.2.4.1 in page 33 in alert standard format specification v2.0 for more details.
w83795g/adg - 85 ? aug/2/2010 revision 1.41 9.1.2 asf register details 9.1.2.1. udid device capability register (udidddevcap) smbus spe cification working group intends to use device capability to distinguish the arbitration priority of generalgetudid() first. thus the very first byte of t he udid is device ca pability, because smbus is a msb first serial protocol and if the client was pulled low, it wins the arbitration. it is set as c1 hex . location: udidddevcap - bank 1 address 20 hex type: read only reset: no reset. default value: c1 hex bit description 7-6 address type. 00 bin = fixed address device. it?s the highest priority device. 01 bin = dynamic and persistent address device. 10 bin = dynamic and volatile address device. if powered-down, the address needs to be reassigned at next power on. the w83795g/adg asf address will be lost if 3vsb does not exist. 11 bin = random number device. (default) 5-1 reserved. 0 pec ? pec support 0 = pec (packet error code) is not supported on this device. 1 = pec is supported on this device. 9.1.2.2. udid version number register (udidversion) this field defi nes the version of udid and silicon for the w83795g/adg. the default is 08 hex. location: udidversion - bank 1 address 21 hex type: read only reset: no reset default value: 08 hex bit description 7-6 reserved. 5-3 udid version. 000 bin = reserved. 001 bin = udid version 1. (default) 010 bin -111 bin = reserved for future use. 2-0 silicon version. for the identification of the w83795g/adg silicon version. 000 bin stands for version a/b.
w83795g/adg - 86 ? aug/2/2010 revision 1.41 9.1.2.3. udid vendor id high/low byte register (udidvendor) this field defi nes nuvoton vendor id. the default is 1050 hex. location: udidvendorh - bank 1 address 22 hex udidvendorl - bank 1 address 23 hex type: read only reset: no reset udidvendorh bit 7 6 5 4 3 2 1 0 name vendor id high byte value 0 0 0 1 0 0 0 0 udidvendorl bit 7 6 5 4 3 2 1 0 name vendor id low byte value 0 1 0 1 0 0 0 0 9.1.2.4. udid device id high/low byte register (udiddev) this field defi nes nuvoton device id. the default is 795a hex. location: udiddevh - bank 1 address 24 hex udiddevl - bank 1 address 25 hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. udiddevh bit 7 6 5 4 3 2 1 0 name device id high byte value 0 1 1 1 1 0 0 1 udiddevl bit 7 6 5 4 3 2 1 0 name device id low byte value 0 1 0 1 1 0 1 0
w83795g/adg - 87 ? aug/2/2010 revision 1.41 9.1.2.5. udid interface high/low byte register (udidif) this field defi nes smbus version and the supported protocol. it is reset to 0024 hex. location: udidifh - bank 1 address 26 hex udidifl - bank 1 address 27 hex type: read write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. udidifh bit 7 6 5 4 3 2 1 0 name reserved value 0 0 0 0 0 0 0 0 udidifl bit 7 6 5 4 3 2 1 0 name reserved ipmi asf oem smbus version value 0 0 1 0 0 1 0 0 bit description 15-7 reserved. 6 ipmi. this device supports additional interface ac cess capability per ipmi specification. 0 = not supported. (default) 1 = supported. 5 asf . this device supports additional interface access capability per asf specification. 0 = not supported. 1 = supported. (default) 4 oem . device supports vendor specific access capability per subsystem vendor id and subsystem device id . 0 = not supported. (default) 1 = supported. 3-0 smbus version. 0 hex = smbus 1.0, not arp available. 1 hex = smbus 1.1, not arp available. 4 hex = smbus 2.0. (default)
w83795g/adg - 88 ? aug/2/2010 revision 1.41 9.1.2.6. udid subsystem vendor id high/lo w byte register (udidsubven) this field defines udid support for subsystems. if no subsystem is supported, it must be written with 0000 hex . it is reset to 0000 hex. location: udidsubvenh - bank 1 address 28 hex udidsubvenl - bank 1 address 29 hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. udidsubvenh bit 7 6 5 4 3 2 1 0 name udid subsystem vendor id high byte value 0 0 0 0 0 0 0 0 udidsubvenl bit 7 6 5 4 3 2 1 0 name udid subsystem vendor id low byte value 0 0 0 0 0 0 0 0 9.1.2.7. udid subsystem device id high/low byte register (udidsubdev) this field defi nes udid support for subsystems. if no subsystem is supported, it must be written with 0000 hex . it is reset to 0000 hex. location: udidsubdevh - bank 1 address 2a hex udidsubdevl - bank 1 address 2b hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. udidsubdevh bit 7 6 5 4 3 2 1 0 name udid subsystem device id high byte value 0 0 0 0 0 0 0 0
w83795g/adg - 89 ? aug/2/2010 revision 1.41 udidsubdevl bit 7 6 5 4 3 2 1 0 name udid subsystem device id low byte value 0 0 0 0 0 0 0 0 9.1.2.8. udid vendor-specific id register (udidspecid) this field defines unique vendor-specific id for differ ent versions of the w83795g/adg. with this field, different w83795g/adg will be identified on the same smbus interface. this register will be loaded with a random number when receiving the reset signal. location: udidspecid4 - bank 1 address 2c hex udidspecid3 - bank 1 address 2d hex udidspecid2 - bank 1 address 2e hex udidspecid1 - bank 1 address 2f hex type: read write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. arp resetdevice command. udidspecid4 ? udidspecid1 bit 7 6 5 4 3 2 1 0 name udid specific vendor id value default value is load from rng 9.1.2.9. random number generator register (rng) the w837 95g/adg internally generates pseudo random numbers by using crc generator and internal clock. due to the deviations of the internal clock, different ic and different power-on time will affect the results of the random numbers. it is reset to ffff hex. location: rng4 - bank 1 address 30 hex rng3 - bank 1 address 31 hex rng2 - bank 1 address 32 hex rng1 - bank 1 address 33 hex type: read only reset: none.
w83795g/adg - 90 ? aug/2/2010 revision 1.41 rng4 ? rng1 bit 7 6 5 4 3 2 1 0 name random number code value random number 9.1.2.10. asf assigned address register (asfadd) after the arp host obtains related device udid, it will start to assi gn each device for later use. the w83 795g/adg will record this assigned address and set it as the default address for asf transactions. it is reset to 00 hex. location: asfadd - bank 1 address 3f hex type: read only reset: 3vsb rising, init reset (cr01.bit7) is set. asfadd bit 7 6 5 4 3 2 1 0 name asf address this register will be assigned while arp assignaddress command issued. value 0 0 0 0 0 0 0 0 9.1.2.11. asf entity/instance registers (enty/entins) the w83 795g/adg supports various channels which can be reported to the host through asf protocol. each sensor channel is associated with an entity (o r location on the motherboard) and entity instance. the table provides an overall look for these register s. the registers are located in bank 1*. *about the bank selection, please refer to the bank select register located at address 00 hex. type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. entity registers: entity of each sensor channel. for other entity types, please refer to pet spec. 03 hex : processor 07 hex : system board. 23 hex : chassis back panel board. nnemonic add (hex) value (hex) description vsen1_enty 40 03 vsen1 entity id vsen2_enty 41 03 vsen2 entity id vsen3_enty - 42-4c 07 vsen3 - vsen13 entity id
w83795g/adg - 91 ? aug/2/2010 revision 1.41 nnemonic add (hex) value (hex) description vsen13_enty vdsen14_enty - vdsen17_enty 4d-50 07 vdsen14 - vdsen17 entity id vtt_enty 51 03 vtt entity id 3vdd_enty 52 07 3vdd entity id 3vsb_enty 53 07 3vdd entity id vbat 54 07 vbat entity id fanin1_enty - fanin14_enty 55-62 07 fanin1 ? fanin14 entity id td1_enty - td4_enty 63-66 07 td1 ? td4 entity id tr1_enty - tr2_enty 67-68 07 tr1 ? tr2 entity id dts1_enty - dts8_enty 69-70 03 dts1 ? dts8 entity id reserved 71 chs_enty 72 23 chassis entity id entity instance registers: nnemonic add (hex) value (hex) description vsen1_ entins 80 01 bit[4:0] is vsen1 entity instance vsen2_ entins 81 02 bit[4:0] is vsen2 entity instance vsen3_ entins - vsen13_entins 82-8c 04-0e bit[4:0] is vsen3 ? vsen13 entity instance vsen9-vsen11 entity functions are not for W83795ADG. vdsen14_ entins - vdsen17_ entins 8d-90 0f-12 bit[4:0] is vdsen14 ? vdsen17 entity instance vtt_ entins 91 03 bit[4:0] is vtt entity instance 3vdd_ entins 92 01 bit[4:0] is 3vdd entity instance 3vsb_ entins 93 02 bit[4:0] is 3vsb entity instance vbat_ entins 94 03 bit[4:0] is vbat entity instance fanin1_entins - fanin2_entins 95 21 bit[7:4] is fanin2 entity instance. bit[3:0] is fanin1 entity instance. fanin3_entins - fanin4_entins 96 43 bit[7:4] is fanin4 entity instance. bit[3:0] is fanin3 entity instance.
w83795g/adg - 92 ? aug/2/2010 revision 1.41 nnemonic add (hex) value (hex) description fanin5_entins - fanin6_entins 97 65 bit[7:4] is fanin6 entity instance. bit[3:0] is fanin5 entity instance. fanin7_entins - fanin8_entins 98 87 bit[7:4] is fanin8 entity instance. bit[3:0] is fanin7 entity instance. fanin9_entins - fanin10_entins 99 a9 bit[7:4] is fanin10 entity instance. bit[3:0] is fanin9 entity instance. fanin11_entins - fanin12_entins 9a cb bit[7:4] is fanin12 entity instance. bit[3:0] is fanin11 entity instance. fanin13_entins - fanin14_entins 9b ed bit[7:4] is fanin14 entity instance. bit[3:0] is fanin13 entity instance. td1_entins - td2_entins 9c 21 bit[7:4] is td2 entity instance. bit[3:0] is td1 entity instance. td3_entins - td4_entins 9d 43 bit[7:4] is td4 entity instance. bit[3:0] is td3 entity instance. tr1_entins - tr2_entins 9e 65 bit[7:4] is tr2 entity instance. bit[3:0] is tr1 entity instance. dts1_entins - dts2_entins 9f 21 bit[7:4] is dts2 entity instance. bit[3:0] is dts1 entity instance. dts3_entins - dts4_entins a0 43 bit[7:4] is dts4 entity instance. bit[3:0] is dts3 entity instance. dts5_entins - dts6_entins a1 65 bit[7:4] is dts6 entity instance. bit[3:0] is dts5 entity instance. dts7_entins - dts8_entins a2 87 bit[7:4] is dts8 entity instance. bit[3:0] is dts7 entity instance. chs_enty a3 17 bit[7:4] is chassis entity instance. bit[3:0] is reserved. 9.1.2.12. power on control option register (pwronoption) the w83795g/adg supports 2 ways to power the system. one is to power the system only one time, no matter 3vdd rises or not. the other is the w83795g/adg continues to issues power-on cycles until it detects 3vdd is already powered on. location: pwronoption - bank 1 address b0 hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set.
w83795g/adg - 93 ? aug/2/2010 revision 1.41 pwronoption bit 7 6 5 4 3 2 1 0 name nuvoton test modes pwr1t value 0 0 0 0 0 0 0 0 bit description 7-0 nuvoton test modes. test modes for production. nuvoton strongly suggests the customer not use these register s to avoid system malfunction. 0 pwr1t ? power on one time. 0 = continues to issue power-on cycles, pw rbtn# assert 0.1sec every 1sec until 3vdd is powered-on. 9.1.2.13. power on command register (pwroncmd) asf remote control command supports remote power on features. here defines the power on commands supported by the w83795g/adg. location: pwroncmd - bank 1 address b1 hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. pwroncmd bit 7 6 5 4 3 2 1 0 name remote power on command value 11 hex 9.1.2.14. power down command register (pwrdncmd) asf remote control command supports remote power down features. here defines the power off commands supported by the w83795g/adg. location: pwrdncmd - bank 1 address b2 hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. pwroffcmd
w83795g/adg - 94 ? aug/2/2010 revision 1.41 bit 7 6 5 4 3 2 1 0 name remote power down command reset 12 hex 9.1.2.15. remote reset command register (rstcmd) asf remote control com mand supports remote re set features. here defines the reset commands supported by the w83795g/adg. location: rstcmd - bank 1 address b3 hex type: read / write reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. rstcmd bit 7 6 5 4 3 2 1 0 name remote reset command reset 10 hex 9.1.2.16. asf test mode (asftm) location: asftm - ban k 1 address b4 hex type: write only reset: 3vsb rising. init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. asftm bit 7 6 5 4 3 2 1 0 name asftm - asf test mode test modes for production. nuvoton strong ly suggests the customer not use these registers to avoid system malfunction. reset ff hex
w83795g/adg - 95 ? aug/2/2010 revision 1.41 10. register summary ? bank2 nnemonic add (hex) por (hex) type description fcms 01/08 00/00 rw fan control mode selection tfmr 02-07 00 rw temperature to fan mapping relationships tss 09-0b 00 rw temperature source selection dfsp 0c 4d rw default fan speed at power-on sfosut 0d 80 rw smartfan output step up time sfosdt 0e 80 rw smartfan output step down time fomc 0f * rw fan output mode control fov 10-17 4d rw or ro fan output value fopfp 18-1f 84 rw fan output pwm frequency prescalar fosv 20-27 30 rw fan output start-up value fonv 28-2f 10 rw fan output nonstop value fost 30-37 ff rw fan output stop time foppc 38 ff rw fan output pwm polarity control fts 40-4f * rw fanin target speed tfts 50 10 rw tolerance of fanin target speed ttti 60-65 28 rw target temperature of temperature inputs ctfs 68-6d 50 rw critical temperature to full speed all fan ht 70-75 53 rw hystersis of temperature sfiv 80-de * rw s mart f an tm iv temperature and dc/pwm registers crpe e0/e1 00 rw configure register of peci error fomv e2-e9 80 rw fan output min value when peci error *: see registers description 10.1.1.1. smart fan setup/status registers in smartfan mode, a specific temperature will be defined in critical temperature to full speed all fan (ctfs) bank2 address 68 hex ? 6d hex. if any temperature input detected is higher than this, all fans will operate at full speed simultaneously. the definiti ons of the control parameters in normal use are shown in the following graph.
w83795g/adg - 96 ? aug/2/2010 revision 1.41 downtime stoptime uptime nonstop start smart fan lowering fanspeed smart fan arising fan speed fanspeed smart fan control parameters figure 10.1.1.2. speed cruise mode eight pairs of fan input sen sor s (fanin8-fanin1) and fan outputs (fanctl8-fanctl1) in fan speed cruise mode. fanctl8-fanctl1 and fanin8-fanin1 mapping are one-by-one relationship. fanctl8 is applies to fanin8. fa nctl7 is applies to fanin7?etc. fanctl3-fanctl8 functions are not for W83795ADG. ? set the fan output (fanctl1 ? fanctl8) controlled mode by fan control mode selection registers (fcms) bank2 address 01 hex and 08 hex ? set fanin target speed (fts) bank2 address 40 hex ? 4f hex ? set tolerance of fanin target speed (tfts) bank2 address 50 hex fan speed cruise mode keeps the fan speed in a spec ified range. first, this range is defined in bios by a fan speed count (the amount of time between clock input signals, not the number of clock input signals in a period of time) and an interval (e.g., 160 10). as long as the fan speed count is in the specified range, fan output remains the same. if t he fan speed count is higher than the high end (e.g., 170), fan output increases to make the count lower. if the fan speed count is lower than the low end (e.g., 150), fan output decreases to make the count higher. one example is illustrated in this figure. 160 170 150 fan output 100 0 50 a c count (%) mechanism of fan speed cruise tm mode
w83795g/adg - 97 ? aug/2/2010 revision 1.41 10.1.1.3. thermal cruise mode therm al cruise mode is an algorithm to control the fan speed to keep the temperature source around the ttti (target temperature of temperature inputs). if the temperature source detects temperatures higher or lower than the target temperatures with ht (hystersis of temperatur e), smart fan control will take actions to speed up or slow down the fan to keep the temperature within the tolerance range. fanctl3-fanctl8 functions are not for W83795ADG. ? the temperature sensor selected by temperature source selection register (tss) bank 2 address 09 hex ? 0b hex ? the fan output (fanctl1 ? fanctl8) selected by temperature to fan mapping relationships register (tfmr) bank2 address 09 hex ? 0b hex ? set the fan output (fanctl1 ? fanctl8) controlled mode by fan control mode selection registers (fcms) bank2 address 01 hex and 08 hex ? set critical temperature to full speed all fan (ctfs) bank2 address 68 hex ? 6d hex ? set target temperature of temperature inputs (ttti) bank2 address 60 hex ? 65 hex ? set hystersis of temperature (ht) bank2 address 70 hex ? 75 hex thermal cruise mode controls the fan speed to keep the temperature in a specified range. first, this range is defined in bios by a temperature and the interval (e.g., 55 c 3 c). as long as the current temperature remains below the low end of this range (i.e., 52 c), the fan is off. once the temperature exceeds the low end, the fan turns on at a speed de fined in bios (e.g., 20% output). thermal cruise mode then controls the fan output ac cording to the current temperatur e. three conditions may occur: (1) if the temperature still exceeds the high end, fan output increases slowly. if the fan is operating at full speed but the temperature still exceeds the high end, a warning message is issued to protect the system. (2) if the temperature falls below the high end (e.g., 58 c) but remains above the low end (e.g., 52 c), fan output remains the same. (3) if the temperature falls below the low end (e.g., 52 c), fan output decreases slowly to zero or to a specified ?stop value?. this stop value is enabled by bank0 index12h, bits 3 ~ 5, and the value itself is specified in bank0 index08h, index09h, index15h and inde x 64h. the fan remains at the stop value for the period of time defined in b ank0 index0ch, index0dh, index17h and index 66h. in general, thermal cruise mode means ? if the current temperature is higher than the high end, increase the fan speed; ? if the current temperature is lower than the low end, decrease the fan speed; ? otherwise, keep the fan speed the same. the following figures illustrate two examples of thermal cruise mode.
w83795g/adg - 98 ? aug/2/2010 revision 1.41 abcd 58c 55c 52c tolerance target temperature tolerance 50 100 0 pwm duty cycle (%) fan start = 20% fan stop = 10% fan start = 20% stop time figure 10-1 mechanism of thermal cruise tm mode (pwn duty cycle) figure 10-2 mechanism of thermal cruise tm mode (dc output voltage)
w83795g/adg - 99 ? aug/2/2010 revision 1.41 10.1.1.4. s mart f an tm iv s mart f an tm iv offers 6 slopes to control the fan speed. there are eight fan outputs and six temperature sensors in s mart f an tm iv mode. fanctl3-fanctl8 functions are not for W83795ADG. ? the temperature sensor selected by temperature source selection register (tss) bank 2 address 09 hex ? 0b hex ? the fan output (fanctl1 ? fanctl8) selected by temperature to fan mapping relationships register (tfmr) bank2 address 09 hex ? 0b hex ? set the fan output (fanctl1 ? fanctl8) controlled mode by fan control mode selection registers (fcms) bank2 address 01 hex and 08 hex ? set critical temperature to full speed all fan (ctfs) bank2 address 68 hex ? 6d hex ? set the relative register-at s mart f an tm iv control mode table ? set hystersis of temperature (ht) bank2 address 70 hex ? 75 hex the 6 slopes can be obtained by setting dc/pwm1~dc/pwm7 and t1~t7 through the registers. when the temperature rises, fan output will calculate the dc/pwm output based on the current slope. for example, in the following figure, t1~t7 ar e the temperature set and dc/pwm1 ~ dc/pwm7 are the fan output set. assume tx is the current te mperature and dc/pwmy is the fan output, then the slope: ( ) ( ) () 45 4/5/ 4 tt pwmdc pwmdc x ? ? = fan output: ( ) ( ) 44 4/ / xttx pwmdc pwmydc ? ? + = fan output dc/pwm1 dc/pwm2 dc/pwm3 dc/pwm4 dc/pwm5 dc/pwm6 dc/pwm7 fullspeed operation hyst. critical hyst. t1 t2 t3 t4 t5 t6 t7 tcritical temperature x1 x4 x5 x3 x2 x6 tx dc/pwmy s mart f an tm iv mechanism
w83795g/adg - 100 ? aug/2/2010 revision 1.41 in addition, s mart f an tm iv can also set up critical tem perature and hysteresis. if the current temperature exceeds critical temperature, fan output outputs dc/pwm7 value, no matter what the slope is. once the temperature ex ceeds critical te mperature, fan output va lue will be determined in accordance to the slope only when the temperature falls below (tcritic al ? criticl hyst.) the right graph gives a picture of how the mapping relationship is made by this setting. in this example, fan2 retrieves information from temperature 1 and temperature 2, and decides the next fan output value applied to fan2. to speed up or to slow down the fan is based on the analysis of the w83795g/adg. basically, the w83795g/adg sorts and analyzes the information from each temperature sensor and smartfan controls. the analysis may be like, ?temperature 1 needs to speed up the fan?; ?temperautre 2 does not need so fast fan speed?; ?temperuatre 1 does not need fast fans any more?, and ?temperautre 2 hopes to keep the current fan speed?. then, the algorithm will make a decision to control the fan by the following simple rule. if temperautre 1 says, ?i need a faster fan?, and temperuatre 2 says, ?no fast fan needed?. the w8 3795g/adg will take request of td1 and start to speed up the fan. in short, the w83795g/adg always takes the most critical request and applies it to the related fan. speed up keep speed speed down targettemp temperature 1 temperature 2 temperature 3 temperature 4 temperature 5 temperature 6 fan1 fan2 fan3 fan4 fan5 fan6 fan7 fan8 any temp request faster fan?? any temp request f hold current speed?? no no speed up hold current speed slow down yes yes
w83795g/adg - 101 ? aug/2/2010 revision 1.41 the concept is quite simple. w hen the temperature is higher than targettemp+ hystersis temp , the fan will be speeded up. when the temperature is lower than targettemp- hystersis temp , the fan will be slowed down. otherwise, the fan keeps its current speed.
w83795g/adg - 102 ? aug/2/2010 revision 1.41 10.1.2 fan register details 10.1.2.1. fan control mode selection registers (fcms) once the smartfan fun ction is enabled, the w83795g/adg supports three smartfan modes, speed cruise tm , thermal cruise tm and s mart f an tm iv mode location: location: fcms1 - bank 2 address 01 hex location: fcms2 - bank 2 address 08 hex type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. fcms1 bit 7 6 5 4 3 2 1 0 name f8sc f7sc f6sc f5sc f4sc f3sc f2sc f1sc default 00 hex bit description 7-0 f8sc ? f1sc: enable fanctl8 ? fanctl1 speed cruise tm mode. 0 = fanctl8 ?fanctl1 is applies fan control by fcms2 register. (default) 1 = fanctl8 ? fanctl1 is applies speed cruise tm control for fanin8-fanin1 speed inputs respectively. fanctl3-fanctl8 functions are not for W83795ADG. fcms2 bit 7 6 5 4 3 2 1 0 name reserved t6fc t5fc t4fc t3fc t2fc t1fc default 00 hex bit description 7-6 reserved. 5-0 t6fc ? t1fc: select temp6 ? temp1 for smart fan mode. 0 = thermal cruise tm mode. 1 = s mart f an tm iv mode. note: see also tfmr (temperature to fan mapping relationships) register. 10.1.2.2. temperature to fan mapping relationships register (tfmr) t1fm r ? t6fmr is six temperature (temp1-temp6) sources to deal with the fan relationship. while reset it is cleared (00 hex ).
w83795g/adg - 103 ? aug/2/2010 revision 1.41 location: t1fmr - bank 2 address 02 hex t2fmr - bank 2 address 03 hex t3fmr - bank 2 address 04 hex t4fmr - bank 2 address 05 hex t5fmr - bank 2 address 06 hex t6fmr - bank 2 address 07 hex type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. t1fmr ? t6fmr bit 7 6 5 4 3 2 1 0 name f8sf f7sf f6sf f5sf f4sf f3sf f2sf f1sf default 00 hex bit description 7-0 f8sf ? f1sf: enable fanctl8 ? fanctl1 smart fan. 0 = fanctl has no relation with this temperature source. fanctl is controlled by manual mode. (default) 1 = applies smartfan control for thermal cruise tm or s mart f an tm iv on fanctl and this temperature. fanctl3-fanctl8 functions are not for W83795ADG. the following example explains the concept of t1fmr ? t6fmr mapping. in this case, t1fmr is set to 86 hex ; t2fmr is set to 52 hex ; t3fmr is set 20 hex , and the other 3 are left unset. temp1fanselect temp2fanselect temp3fanselect temp4fanselect temp5fanselect temp6fanselect split into 1 0 0 0 0 0 fan8 0 1 0 0 0 0 fan7 0 0 1 0 0 0 fan6 0 1 0 0 0 0 fan5 0 0 0 0 0 0 fan4 1 0 0 0 0 0 fan3 1 1 0 0 0 0 fan2 0 0 0 0 0 0 fan1 1 0 0 0 0 0 fan8 0 1 0 0 0 0 fan7 0 0 1 0 0 0 fan6 0 1 0 0 0 0 fan5 0 0 0 0 0 0 fan4 1 0 0 0 0 0 fan3 1 1 0 0 0 0 fan2 0 0 0 0 0 0 fan1 temp1 temp2 temp3 temp4 temp5 temp6 rotate 1 0 0 0 0 0 fan8 0 1 0 0 0 0 fan7 0 0 1 0 0 0 fan6 0 1 0 0 0 0 fan5 0 0 0 0 0 0 fan4 1 0 0 0 0 0 fan3 1 1 0 0 0 0 fan2 0 0 0 0 0 0 fan1 temp1 temp2 temp3 temp4 temp5 temp6 splitting and rotating the six registers bit by bit as the figure above helps to understand the relationship better. for the rows of fan1 and fan4, all of the temperatures are de-asserted, which means fan1/fan4 and the temperature are irrelev ant. thus they are in the manual mode under this setting. for fan2, it is clear that it is relative to temper ature 1 and 2, so it will activate smartfan control with temperature 1/2 as its input.
w83795g/adg - 104 ? aug/2/2010 revision 1.41 10.1.2.3. temperature source selection register (tss) w83 795g/adg has six temperature sources (temp1- temp6) to control smartfan mode, user can select thermal cruise mode or s mart f an tm iv. location: t12tss - bank 2 address 09 hex t34tss - bank 2 address 0a hex t56tss - bank 2 address 0b hex type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. t12tss bit 7 6 5 4 3 2 1 0 name temp2 temperature source selection bit [3-0] refer the temperature source selection table to select temperature source. temp1 temperature source selection bit [3-0] refer the temperature source selection table to select temperature source. default 00 hex t34tss bit 7 6 5 4 3 2 1 0 name temp4 temperature source selection bit [3-0] refer the temperature source selection table to select temperature source. temp3 temperature source selection bit [3-0] refer the temperature source selection table to select temperature source. default 00 hex t56tss bit 7 6 5 4 3 2 1 0 name temp6 temperature source selection bit [3-0]. refer the temperature source selection table to select temperature source. temp5 temperature source selection bit [3-0] refer the temperature source selection table to select temperature source. default 00 hex temperature source selection table: temperature source bit [3-0] temp1 temp2 temp3 temp4 temp5 temp6 0000 bin td1/tr1 td2/tr2 td3/tr3 td4/tr4 tr5 tr6 0001 bin dts1 dts2 dts3 dts4 td1/tr1 td2/tr2 0010 bin dts5 dts6 dts7 dts8 td3/tr3 td4/tr4 0011 bin tr5 tr6 tr5 tr6 reserved reserved 0100 bin -1111 bin 127 127 127 127 127 127
w83795g/adg - 105 ? aug/2/2010 revision 1.41 10.1.2.4. default fan speed at power-on (dfsp) dfsp ( defa ult fan peed at power-on) sets the initial speed of every fan. when the system is turned on, a default will be given to all fan outputs according to the register content. this register is specially designed to be reset by vsb only, so at the second system po wer on, the system w ill use the last setup speed to turn on all of the fans. location: dfsp - bank 2 address 0c hex type: read / write reset: 3vsb rising, dfsp bit 7 6 5 4 3 2 1 0 name defaultspeed (default fan speed at power-on). spec ifies the fan duty at next power on. default 4d hex 10.1.2.5. smartfan output step up time (sfosut) sfosut adj usts the time interval of the fan speed up by a unit. the default setting is 12.8sec. location: sfosut - bank 2 address 0d hex type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. sfosut bit 7 6 5 4 3 2 1 0 name uptime (smartfan step up time). unit in 0. 1sec. programmed as the interval of continuous fan ramping up. default 80 hex smartfan is designed for the smooth operation of t he fan. the fan duty is seldom suddenly increased or decreased. instead, most often the duty is incr eased or decreased by 1 ls b. the up time / down time register defines the time interval between succ essive duty increases or decreases. if this value is set too small, the fan will not have enough time to speed up after tuning the duty and sometimes may result in unstable fan speed. on the other hand, if up time / down time is set too large, the fan may not work fast enough to dissipate the heat. this register should never be set to 0 . otherwise, the fan duty will be abnormal. only in the following cases w ill the fan duty soar or plummet. ? 3vdd power ? on/off ? fan turn off state to start ? fan at fonv (fan output nonstop value) to turn off state 10.1.2.6. smartfan output step down time (sfosdt)
w83795g/adg - 106 ? aug/2/2010 revision 1.41 down time reduces the time interval of the fastes t fan speed by a unit. the default setting is 12.8sec. location: sfosdt - bank 2 address 0e hex type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. sfosut bit 7 6 5 4 3 2 1 0 name downtime (smartfan step down time). unit in 0. 1sec. programmed as the interval of continuous fan ramping down. default 80 hex this register should never be set to 0 . otherwise, the fan duty will be abnormal. 10.1.2.7. fan output mode control (fomc) location: fomc - bank 2 address 0f hex type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. fomc bit 7 6 5 4 3 2 1 0 name f8omc f7omc f6omc f5omc f4omc f3omc f2omc f1omc default w83795g default value is 00 hex W83795ADG default value is 02 hex bit description 7-0 f8omc ? f1omc: fanctl8 ? fanctl1 output mode control. 0 = pwm output duty cycle. (default) 1 = dc output. fanctl3-fanctl8 functions are not for W83795ADG. 10.1.2.8. fan output value (fov)
w83795g/adg - 107 ? aug/2/2010 revision 1.41 f1ov ? f8ov is fanctl1-fanctl8 current fan output. in the manual mode, the user can set preferred fan output value. however, in the smart fan mode, it is read-only. fans that are not set to be in speed cruise tm , thermal cruise tm or s mart f an tm iv are in manual mode. location: f1ov - bank 2 address 10 hex f2ov - bank 2 address 11 hex f3ov - bank 2 address 12 hex f4ov - bank 2 address 13 hex f5ov - bank 2 address 14 hex f6ov - bank 2 address 15 hex f7ov - bank 2 address 16 hex f8ov - bank 2 address 17 hex type: read / write (in manual mode) read only (in the smart fan mode) reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. f1ov ? f8ov bit 7 6 5 4 3 2 1 0 name output value default depend on defaultspeed . 4d hex. bit description 7-0 output value ? current fan output value. specifies the current fan output value of the fan (fanctl8-fanctl1). if 3vdd is low, this register is set to zero by the hardware. fanctl3-fanctl8 functions are not for W83795ADG. f1ov ? f8ov also has a special characteristic- sequential power-on respectively. this function is used to avoid over loads of the system current when the system is powered-on and all fans start to spin. the w83795g/adg takes 0.1 second (12.5ms intervals for 8 fans) to turn on all of the fans one by one. 10.1.2.9. fan output pwm frequency prescalar (fopfp) f1opfp ? f8 opfp control the fanctl1-fanctl8 fan outpu t frequency in the pwm mode. a wide range of clocks can be selected to satisfy customer needs. the default output frequency is 26 khz. fanctl3-fanctl8 functions are not for W83795ADG. location:
w83795g/adg - 108 ? aug/2/2010 revision 1.41 f1opfp - bank 2 address 18 hex f5opfp - bank 2 address 1c hex f2opfp - bank 2 address 19 hex f6opfp - bank 2 address 1d hex f3opfp - bank 2 address 1a hex f7opfp - bank 2 address 1e hex f4opfp - bank 2 address 1b hex f8opfp - bank 2 address 1f hex type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. f1opfp ? f8opfp bit 7 6 5 4 3 2 1 0 name cksel divisor default 1 0 0 0 0 1 0 0 * the default value of b version w83795g/adg is 85h. bit description 7 cksel ? clock source select. clkin frequency clksel 14.318mhz 24mhz 33mhz 48mhz 0 1.024khz 1.024khz 1.024khz 1khz 1 55.93kz 93.75khz 130.21khz 125khz 6-0 divisor ? clock frequency divisor. the clock source select ed by cksel will be divided by the di visor and used as a fan pwm output frequency. there are 2 di visors depending on cksel. if cksel equals 1, then the output clock is simply equal to 130.21/ (d ivisor+1) khz (@ frequency of clkin is 33mhz). if cksel equals 0, the output clock is 1khz/map peddivisor. mappeddivisor depends on divi sor[3:0] and is described in the table below. divisor[3:0] mapped divisor output frequency divisor[3:0] mapped divisor output frequency 0000 1 1024hz 1000 12 85hz 0001 2 512hz 1001 16 64hz 0010 3 341hz 1010 32 32hz 0011 4 256hz 1011 64 16hz 0100 5 205hz 1100 128 8hz 0101 6 171hz 1101 256 4hz 0110 7 146hz 1110 512 2hz 0111 8 128hz 1111 1024 1hz 10.1.2.10. fan output start-up value (fosv)
w83795g/adg - 109 ? aug/2/2010 revision 1.41 from still to rotate, the fan usually needs a higher fan output value to generate enough torque to conquer the restriction force. t hus the w83795g/adg includes a fosv (fan output start-up value) to turn on the fan with the specified output value. (please refer to smart fan control parameters figure) location: f1osv - bank 2 address 20 hex f2osv - bank 2 address 21 hex f3osv - bank 2 address 22 hex f4osv - bank 2 address 23 hex f5osv - bank 2 address 24 hex f6osv - bank 2 address 25 hex f7osv - bank 2 address 26 hex f8osv - bank 2 address 27 hex type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. f1osv ? f8osv bit 7 6 5 4 3 2 1 0 name fanstart default 30 hex bit description 7-0 fanstart ? control the fanctl1-fanctl8 fan output start-up value. fanctl3-fanctl8 functions are not for W83795ADG. 10.1.2.11. fan output nonstop value (fonv) it takes so me time to bring a fan from still to working state. therefore, f1onv - f8onv are designed with a minimum fan output to keep the fan workin g when the system does not require the fan to help reduce heat but still want to keep the fast respon se time to speed up the fan. (please refer to smart fan control parameters figure) location: f1onv - bank 2 address 28 hex f2onv - bank 2 address 29 hex f3onv - bank 2 address 2a hex f4onv - bank 2 address 2b hex f5onv - bank 2 address 2c hex f6onv - bank 2 address 2d hex f7onv - bank 2 address 2e hex
w83795g/adg - 110 ? aug/2/2010 revision 1.41 f8onv - bank 2 address 2f hex reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. f1onv ? f8onv bit 7 6 5 4 3 2 1 0 name fannonstop default 10 hex bit description 7-0 fannonstop ? control the fanctl1-fanctl8 f an output nonstop value. fanctl3-fanctl8 functions are not for W83795ADG. 10.1.2.12. fan output stop time (fost) a time interval is spe cified to tell the w83795g/adg when to turn off the fan if smartfan continuously requests to slow down the f an which has already reached the f1onv ? f8onv . the default is 10 sec. (please refer to smart fan control parameters figure) location: f1ost - bank 2 address 30 hex f2ost - bank 2 address 31 hex f3ost - bank 2 address 32 hex f4ost - bank 2 address 33 hex f5ost - bank 2 address 34 hex f6ost - bank 2 address 35 hex f7ost - bank 2 address 36 hex f8ost - bank 2 address 37 hex reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. f1ost ? f8ost bit 7 6 5 4 3 2 1 0 name fanstoptime default ff hex bit description
w83795g/adg - 111 ? aug/2/2010 revision 1.41 7-0 fanstoptime ? control the fanctl1-fanctl8 fan stop time from fonv (fan output nonstop value) to the off state. unit in 0.1sec. ranges from 0.1sec to 25.5sec. if set to 0, the fan will never stop. fanctl3-fanctl8 functions are not for W83795ADG. 10.1.2.13. fan output pwm polarity control (foppc) location: foppc - bank 2 address 38 hex reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. foppc bit 7 6 5 4 3 2 1 0 name f8pol f7pol f6pol f5pol f4pol f3pol f2pol f1pol default ff hex bit description 7-0 f8pol ? f1pol: control fanctl8 - fanct l1 pwm output polarity. 0 = low active. pwm is contro lled by negative duty cycle. 1 = high active. (default). pwm is controlled by positive duty cycle. fanctl3-fanctl8 functions are not for W83795ADG. 10.1.2.14. fanin target speed (fts) in fan speed cruise tm mode, each fanin tachometer has to have a target fan speed. the w83795g/adg will try to tune relative fan output to keep the fan speed of target. the default target speed for fanin tachometer is 6000h. location: f1tsh - bank 2 address 40 hex f1tsl - bank 2 address 41 hex f2tsh - bank 2 address 42 hex f2tsl - bank 2 address 43 hex f3tsh - bank 2 address 44 hex f3tsl - bank 2 address 45 hex f4tsh - bank 2 address 46 hex f4tsl - bank 2 address 47 hex f5tsh - bank 2 address 48 hex f5tsl - bank 2 address 49 hex f6tsh - bank 2 address 4a hex f6tsl - bank 2 address 4b hex f7tsh - bank 2 address 4c hex f7tsl - bank 2 address 4d hex f8tsh - bank 2 address 4e hex
w83795g/adg - 112 ? aug/2/2010 revision 1.41 f8tsl - bank 2 address 4f hex type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. f1tsh ? f8tsh bit 7 6 5 4 3 2 1 0 name f1tsh ? f8tsh : fanin1 ? fanin8 tachometer target speed high byte. the real fanin rpm value calculation is referred to fanin count caclulation description. 12-bitcount value bit[11:4] default 60 hex f1tsl ? f8tsl bit 7 6 5 4 3 2 1 0 name f1tsl ? f8tsl : fanin1 ? fanin8 tachometer target speed low byte. 12-bitcount value bit [3:0] reserved. default 00 hex see also: tfts and fan speed cruise tm 10.1.2.15. tolerance of fanin target speed (tfts) location: tfts - bank 2 address 50 hex type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. tfts bit 7 6 5 4 3 2 1 0 name reserved tolerance of fanin target speed default 0 0 0 1 0 0 0 0 bit description 7-6 reserved. 5-0 tolerance of fanin target speed
w83795g/adg - 113 ? aug/2/2010 revision 1.41 tolerance of fanin1 ? fanin8 tachometer target speed. tolerance range is 00h~3fh 10.1.2.16. target temperature of temperature inputs (ttti) in thermal cruise tm mode, each temperature source has to have a target temperature. the w83795g/adg will try to tune the fan output to keep the temperature of the target device around the target temperature. the default target temperature is 40 . location: t1tti - bank 2 address 60 hex t2tti - bank 2 address 61 hex t3tti - bank 2 address 62 hex t4tti - bank 2 address 63 hex t5tti - bank 2 address 64 hex t6tti - bank 2 address 65 hex type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. t1tti ?t6tti bit 7 6 5 4 3 2 1 0 name reserved target temperature. default 0 28 hex (40 ) bit description 7 reserved. 6-0 target temperature. temp1 ? temp6 target temperature inputs. unit in see also: ht and thermal cruise tm 10.1.2.17. critical temperature to full speed all fan (ctfs) ctfs defin es a system critical temperature. temp eratures exceeding this threshold may lead to system damage or crash. when the w83795g/ad g detects any temperature input exceeding ctfs , it will speed up all of the fans to lower the temperature. when the temperature exceeds critical temperature, all fanout influenced by this temperature will have a 100% output duty. the other fanout will not have 100% duty.
w83795g/adg - 114 ? aug/2/2010 revision 1.41 location: t1ctfs - bank 2 address 68 hex t2ctfs - bank 2 address 69 hex t3ctfs - bank 2 address 6a hex t4ctfs - bank 2 address 6b hex t5ctfs - bank 2 address 6c hex t6ctfs - bank 2 address 6d hex type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. t1ctfs ? t6ctfs bit 7 6 5 4 3 2 1 0 name critical temperature default 50 hex (80 ) bit description 7-0 critical temperature. temp1 ? temp6 temperature exceed the crit ical temperature, fanctl8 ? fanctl1 will work at full speed. unit in . the range is 0 ~127. fanctl3-fanctl8 functions are not for W83795ADG. 10.1.2.18. hystersis of temperature (ht) in thermal cruise and s mart f an tm iv mode, to prevent unstable temper atures from throttling the fan speed, the w83795g/adg employs a hysteresis temperature to separate the speed-up/slow-down temperature points. location: ht1 - bank 2 address 70 hex ht2 - bank 2 address 71 hex ht3 - bank 2 address 72 hex ht4 - bank 2 address 73 hex ht5 - bank 2 address 74 hex ht6 - bank 2 address 75 hex type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set,
w83795g/adg - 115 ? aug/2/2010 revision 1.41 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. ht1 ? ht6 bit 7 6 5 4 3 2 1 0 name hysteresis of critical temperature hysteresis of operation temperature default 5 hex (5 ) 3 hex (3 ) bit description 7-5 hysteresis of critical temperature. hysteresis of critical temperature te mp1-temp6 temperature. the range is 0 ~15 4-0 hysteresis of operation temperature. hysteresis of operation te mperature for smart fan tm iv and thermal cruise tm temp1-temp6 temperature. the range is 0 ~15 10.1.2.19. s mart f an tm iv temperature and dc/pwm registers (sfiv) s mart f an tm iv is an algorithm providing a table mapping mechanism to translate the temperature information into output fan duties. the mapping table requires 2 domains for the translation. in the table, a certain temperature corres ponds to a certain duty. t1-t7 (temperature) and dc/pwm1-dc/pwm7 (dc/pwm fan output values) are used to define the t able. there are totally six tables reside in the w83795g/adg, one table per temperature chan nel and 7 entries per table. therefore, t1-t7 will have 42 registers, and another 42 registers for dc/pwm1-dc/pwm7 in this and next section location: relative register-at s mart f an tm iv control mode table relative temperautre nnemonic add (hex) por (hex) type t1 ? t7 80-86 00 rw temp1 dc/pwm1 ? dc/pwm7 88-8e ff rw t1 ? t7 90-96 00 rw temp2 dc/pwm1 ? dc/pwm7 98-9e ff rw t1 ? t7 a0-a6 00 rw temp3 dc/pwm1 ? dc/pwm7 a8-ae ff rw t1 ? t7 b0-b6 ff rw temp4 dc/pwm1 ? dc/pwm7 b8-be ff rw t1 ? t7 c0-c6 ff rw temp5 dc/pwm1 ? dc/pwm7 c8-ce ff rw t1 ? t7 d0-d6 ff rw temp6 dc/pwm1 ? dc/pwm7 d8-de ff rw
w83795g/adg - 116 ? aug/2/2010 revision 1.41 reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. t1 ? t7 bit 7 6 5 4 3 2 1 0 name s mart f an tm iv temperature default 00 hex (0 ) dc/pwm1 ? dc/pwm7 bit 7 6 5 4 3 2 1 0 name s mart f an tm iv dc/pwm default ff hex (0 ) 10.1.2.20. configure register of peci error (crpe) location: crpe1 - ba nk 2 address e0 hex crpe2 - bank 2 address e1 hex type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. crpe1 bit 7 6 5 4 3 2 1 0 fanctl4 bit[1-0] fanctl3 bit[1-0] fanctl2 bit[1-0] fanctl1 bit[1-0] name refer the peci error condition table to fan output value. default 00 hex crpe2 bit 7 6 5 4 3 2 1 0 fanctl8 bit[1-0] fanctl7 bit[1-0] fanctl6 bit[1-0] fanctl5 bit[1-0] name refer the peci error condition table to fan output value. default 00 hex
w83795g/adg - 117 ? aug/2/2010 revision 1.41 peci error condition table: fanctl1-fanctl8 fan output value. fanct l3-fanctl8 functions are not for 83795adg. bit [1-0] peci error condition 00 bin fan output value keeps at its current value. 01 bin fan output value will be set to fomv (fan output min value when peci error). 1x bin fan output value will be set to the full speed value (ffh). 10.1.2.21. fan output min value when peci error (fomv) location: f1omv - ban k 2 address e2 hex f2omv - bank 2 address e3 hex f3omv - bank 2 address e4 hex f4omv - bank 2 address e5 hex f5omv - bank 2 address e6 hex f6omv - bank 2 address e7 hex f7omv - bank 2 address e8 hex f8omv - bank 2 address e9 hex reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. f1omv ? f8omv bit 7 6 5 4 3 2 1 0 name fanmin default 80 hex bit description 7-0 fanmin ? control the fanctl1-fanctl8 fan output min value when peci error condition is occurred. also see crpe (configure register of peci error) fanctl3-fanctl8 functions are not for W83795ADG.
w83795g/adg - 118 ? aug/2/2010 revision 1.41 11. peci control and sb-tsi function 11.1 peci control registers intel? new generation cpus such as presler begin to support new single wire digital temperature monitoring interface which is called p latform e nvironment c ontrol i nterface or peci. the w83795g/adg supports the peci* version 2.0 fo r these new generation cpus. all peci control registers are located in bank 3. the w83795g/adg peci configuration, including the peci address and number of domains, must match the cpu type. bios have to detect which kind of cpu it is and program the correct configuration in the w83795g/adg. peci (platform environment control interface) is a new digital interface to read the cpu temperature of intel? cpus. with a bandwidth ranging from 2 kbps to 2 mbps, peci uses a single wire for self-clocking and data transfer. by interfacing to the digital thermal sensor (dts) in the intel? cpu, peci reports a negative temperature (in counts) relati ve to the processor?s temperature at which the thermal control circuit (tcc) is activated. at the tcc activation temperature, the intel cpu will operate at reduced performance to prevent the device from thermal damage. peci is one of the temperature sensing me thods that the w83795g/adg supports. the w83795g/adg contains a peci master and reads the cpu peci temperature. the cpu is a peci client. the peci temperature values returning from the cpu are in ?counts? which ar e approximately linear in relation to changes in temperature in degrees cent igrade. however, this linearity is approximate and cannot be guaranteed over the entire range of peci temp eratures. for further information, refer to the peci specification. all references to ?temperature? in this section are in ?counts? instead of ? c?. figure-1 sh ows a typical fan speed (pwm duty cycle) and peci temperature relationship. figure-1 peci temperature
w83795g/adg - 119 ? aug/2/2010 revision 1.41 in this illustration, when peci temper ature is -20, the pwm duty cycle fo r fan control is at duty2. when cpu is getting hotter and the peci temperature is -10, the pwm duty cycle is at duty1. at tcontrol peci temperature, the recommendation fr om intel is to operate the cpu fan at full speed. therefore duty1 is 100% if this recommendation is followed. the value of tcontrol can be obtained by reading the related machine specific register (msr ) in the intel cpu. the tcontrol msr address is usually in the bios writer?s guide for the cpu fa mily in question. refer to the relevant cpu documentation from intel for more informati on. in this example, tcontrol is -10. when the peci temperature is below -20, the duty cycle is fixed at duty2 to maintain a minimum (and constant) rpm for the cpu fan. w83795g/adg?s fan control circuit can only accept positive real-time temperature inputs and limits setting (in smart fan ? mode). the device provides offset registers to ?shift? the negative peci readings to positive values otherwise the fan cont rol circuit will not function properly. the offset registers are the tbase r egisters located at logical device c, cr[e1h]~cr[e4h ]. these registers should be programmed with (positive) values so that the resultant value (tbase + peci) is always positive. the unit of the tbase register contents is ?count? to match t hat of peci values. the resultant value (tbase + peci) should not be interpreted as the ?temperature? (whether in count or c) of the peci client (cpu). figure-2 sh ows the temperature/fan speed relationship after tbase offsets are applied (based on figure-1 ). th is view is from the perspective of the w83795g/adg fan control circuit. figure-2 temperature and fan speed relation after tbase offsets assuming tbase is set to 100 and the peci temperature is -15 , the real-time temperature value to the fan control circuit will be 85 (-15 + 100). the value of 55 (hex) will appear in the relevant real-time temperature register. while using smart fan control function of w83795g/adg, bios/software must include tbase in determining the thresholds (limits). in this example, assuming tcontrol is -10 and tbase is set to 100 (1) ,
w83795g/adg - 120 ? aug/2/2010 revision 1.41 the threshold temperature value corresponding to t he ?100% fan duty cycle? event is 90 (-10+100). the value of 5a (hex) should be written to the relevant threshold register. (1) tcontrol is typically -10 to -20 for peci-enabled cpus. base on that, a value of 85 ~100 for tbase could be set for proper operation of the fan control circuit. this recommendation is applicable for most designs. in general, the concept presented in this section could be used to determine the optimum value of tcontrol to match the specific application.
w83795g/adg - 121 ? aug/2/2010 revision 1.41 11.2 sb temperature sensor interface (sb-tsi) the w83795g/adg is equipped with a built-in temperature sensor which uses the sbi temperature sensor interface (sb-tsi) interface. sb-tsi function is not for W83795ADG. the sb-tsi largely follows smbus v2.0 specification except: z the statement ?an smbus device must always acknowledge (ack) its own address ?does not apply since a processor may nack on repeated star t conditions even if the address matches its own smbus address. z only 7-bits smbus addresses are supported. z sb-tsi implements the send/receive byte and read/write byte protocols. z sb-tsi registers can only by written using a write byte command. z address resolution protocol (arp) is not implemented. z packet error checking (pec) is not supported. figure-3 sb-tsi illustration sb-tsi temperature readings and limit registers enc ode the temperature in increments of one eighth of a degree from 0 to 255.875. the high byte represents the integer portion of the temperature from 0 to 255. one increment in the high byte is equivalent to a step of 1 c. the upper three bits of the low byte represent the decimal portion of the temperature. one increment of these bits is equivalent to a step of 0.125 c. w83795g cpu sb-tsi fan control sb-tsi host tsic tsid
w83795g/adg - 122 ? aug/2/2010 revision 1.41 table-1 sb-tsi temperature encoding examples temperature temperature high byte temperature low byte 0.000 c 0000_0000b 0000_0000b 1.000 c 0000_0001b 0000_0000b 25.125 c 0001_1001b 0010_0000b 50.500 c 0011_0010b 1000_0000b 127.875 c 0111_1111b 1110_0000b 128.000 c 1000_0000b 0000_0000b 255.875 c 1111_1111b 1110_0000b
w83795g/adg - 123 ? aug/2/2010 revision 1.41 12. register summary ? bank3 nnemonic add (hex) por (hex) type description dtsc 01 00 rw digital temperature sensor configuration dtse 02 00 rw digital temperature sensor enable pcr 10 84 rw peci control register watp 13 81 rw waiting available time for peci 1.1 only pac 16-18 * rw peci agent configuration register prts 19-1a 00 rw peci report temperature style pmmc 1b-1d * rw peci manual mode control registers patb 20-27 00 rw peci agent tbase temperature registers gdc 30-37 00 ro getdib command acr 38-3a * ro agent characteristic registers artr 40-5f * ro agent relative temperature registers attr 60-6f * ro agent tcontrol temperature registers pcar 70-73 00 rw pci configuration address registers pcwd 74-77 00 rw pci configuration write data pcrd 78-7b 00 ro pci configuration read data msc 80-84 00 rw mbxsend command cc 85 00 ro completion code mgc 86-8a 00 ro mbxget command stcr a0 10 rw sb-tsi configuration register starp a1 19 rw sb-tsi auto read period stse a2 00 ro sb-tsi slave enable stoss a3 00 rw sb-tsi one shot start register stmmcr a4-a6 * rw sb-tsi manual mode configuration registers strd a8 00 ro sb-tsi read data *: see registers description
w83795g/adg - 124 ? aug/2/2010 revision 1.41 12.1 digital temperature sensor configuration (dtsc) location: dtsc - bank 3 address 01 hex type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. dtsc bit 7 6 5 4 3 2 1 0 name sr reserved dis default 00 hex bit description 7 software reset. (sr) 0 = pwm output duty cycle. (default) 1 = software reset intel peci or amd sb-tsi interface. 6-1 reserved. 0 dts interface select. (dis) 0 = intel peci. (default) 1 = amd sb-tsi. 12.2 digital temperature sensor enable (dtse) location: dtse - bank 3 address 02 hex type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. dtse bit 7 6 5 4 3 2 1 0 name d8e d7e d6e d5e d4e d3e d2e d1e default 00 hex bit description 7 dts8 enable (d8e)
w83795g/adg - 125 ? aug/2/2010 revision 1.41 bit description 0 = disable. (default) 1 = enable. in intel peci, dts8 device address is 37h. in amd sb-tsi, dts8 slave address is 96h. 6 dts7 enable (d7e) 0 = disable. (default) 1 = enable. in intel peci, dts7 device address is 36h. in amd sb-tsi, dts7 slave address is 94h. 5 dts6 enable (d6e) 0 = disable. (default) 1 = enable. in intel peci, dts6 device address is 35h. in amd sb-tsi, dts6 slave address is 92h. 4 dts5 enable (d5e) 0 = disable. (default) 1 = enable. in intel peci, dts5 device address is 34h. in amd sb-tsi, dts5 slave address is 90h. 3 dts4 enable (d4e) 0 = disable. (default) 1 = enable. in intel peci, dts4 device address is 33h. in amd sb-tsi, dts4 slave address is 9eh. 2 dts3 enable (d3e) 0 = disable. (default) 1 = enable. in intel peci, dts3 device address is 32h. in amd sb-tsi, dts3 slave address is 9ch. 1 dts2 enable (d2e) 0 = disable. (default) 1 = enable. in intel peci, dts2 device address is 31h. in amd sb-tsi, dts2 slave address is 9ah. 0 dts1 enable (d1e) 0 = disable. (default) 1 = enable. in intel peci, dts1 device address is 30h. in amd sb-tsi, dts1 slave address is 98h.
w83795g/adg - 126 ? aug/2/2010 revision 1.41 12.3 peci control register (pcr) location: pcr - bank 3 address 10 hex type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. pcr bit 7 6 5 4 3 2 1 0 name mmc atr adj epf en_peci default 84 hex bit description 7 manual mode command. (mmc) 0 = auto repeat. 1 = manual mode command only do one time (default) 6-5 adjust transaction tbit rate. (atr) clkin 14.318mhz 24mhz 33mhz 48mhz 00 bin tbit = 1.1us tbit = 0.67us tbit = 0.5us tbit = 0.5us 01 bin tbit = 2.2us tbit = 1.33us tbit = 1us tbit = 1us 10 bin tbit = 4.5us tbit = 2.67us tbit = 2us tbit = 2us 11 bin tbit = 8.9us tbit = 5.33us tbit = 4us tbit = 4us 4-2 compensate the effect of rising time on physical bus. (adj) adjusting the tbit counter number to adapt the various agent loading default is 001 bin (ideal timing : 001) 1 enable peci 1.1a function. (epf) 0 = disable peci1.1a function. 1 = enable peci 1.1a function. peci_req# function is enabled. enable fanin11/peci_req#/pvid2/gpio3 multi-function pin for peci1.1a. vid function is not for W83795ADG. 0 enable peci host function. (en_peci) read only. if enable digital temperautre sensor enable (dtse) & dts interface select (dis) bit =0, peci host function will be enabled and en_peci will be set to "1".
w83795g/adg - 127 ? aug/2/2010 revision 1.41 12.4 waiting available time for peci 1.1 only (watp) location: watp - bank 3 address 13 hex type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. the command will be sent 2ms (default) after peci_re quest is pulled low. the time interval can be adjusted by setting this register. watp bit 7 6 5 4 3 2 1 0 name wait_ava_time [7:0] default 81 hex 12.5 peci agent configuration registers (pac) this register commands the peci host to process related agents and domains. only the agent or domain specified in this register will pr ocess peci transactions . it is reset to 00 hex . location: pac1 - bank 3 address 16 hex pac2 - bank 3 address 17 hex pac3 - bank 3 address 18 hex type: read / write reset: 3vsb rising, pac1 - bank 3 address 16 hex bit 7 6 5 4 3 2 1 0 name a8d1 a7d1 a6d1 a5d1 a4d1 a3d1 a2d1 a1d1 default ff hex bit description 7-0 agent 8 ? agent1 domain 1 enable bit. (a8d1 ? a1d1) 0 = agent does not have domain 1. 1 = agent has domain 1. (default)
w83795g/adg - 128 ? aug/2/2010 revision 1.41 pac2 - bank 3 address 17 hex peci host to process related agents version (1.0 or 2.0). bit 7 6 5 4 3 2 1 0 name a8p2 a7p2 a6p2 a5p2 a4p2 a3p2 a2p2 a1p2 default 00 hex bit description 7-0 agent 8 ? agent1 peci2.0 enable. (a8p2 ? a1p2) 0 = agent does not supply peci 2.0. (default) 1 = agent supplies peci 2.0. pac3 - bank 3 address 18 hex bit 7 6 5 4 3 2 1 0 name reserved peci_dc manual_dmn1 manual_ver20 default 00 hex bit description 7-3 reserved. 2 adjust peci tbit duty cycle selection. (peci_dc) 0 = 75% tbit high duty cycle time. (default) 1 = 68% tbit high duty cycle time. 1 external control of 2domains. (manual_dmn1) enable external control of domain1 existence 0 = disable. (default) 1 = enable. 0 external control of version 2.0. (manual_ver20 ) enable external control of peci 2.0 version 0 = disable. (default) 1 = enable. 12.6 peci report temperature style registers (prts) location: prts1 - bank 3 address 19 hex prts2 - bank 3 address 1a hex type: read / write
w83795g/adg - 129 ? aug/2/2010 revision 1.41 reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. prts1 - bank 3 address 19 hex bit 7 6 5 4 3 2 1 0 name reserved clamp rthigh default 00 hex bit description 7-2 reserved. 1 peci clamping function to filter the unreasonable dts value. (clamp) 0 = dts values are fully transparent. 1 = dts values are clamped in -128 ~ 0. 0 return high temperature of doamin0 or domain1. (rthigh) return agent higher temperature between domain0 and domain1 0 = the temperature of each agent is returned from domain 0 or domain 1, which is controlled by prts2 (bank 3 address 1a hex ) 1 = return the highest temperature in domain 0 and domain 1 of individual agent. prts2 - bank 3 address 1a hex bit 7 6 5 4 3 2 1 0 name a8rt a7rt a6rt a5rt a4rt a3rt a2rt a1rt default 00 hex bit description 0 agent 8 ? agent 1 always return the relative temperature. (a8rt-a1rt) report specific domain temperature for individual agent. it is only available when rthigh = 0. 0 = agent always returns the relative temperature from domain 0. 1 = agent always returns the relative temperature from domain 1. 12.7 peci manual mode control registers (pmmc) type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set,
w83795g/adg - 130 ? aug/2/2010 revision 1.41 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. mm1 (manual mode 1) - bank 3 address 1b hex bit 7 6 5 4 3 2 1 0 name reserved auto pbc md ma default 40 hex bit description 7 reserved. 6 command code assignment mode. (auto) 0 = disable. 1 = automatically assign comma nd code for transportation. 5-4 pcibytecount[1:0] (pbc) indicate how many data bytes would be delivered or received in pciconfig command. 00:1 byte, 01: 2 bytes, 10:4 bytes the number of data byte for pciwr() and pcird() commands. 00 bin = one byte. 01 bin = two bytes. 10 bin = four bytes. 3 manual_domain. (md) 0: manual command execution will target domain0. in other word, 1 for domain1 2-0 manual_agent[2:0] (ma) 000 bin = manual command execution will target agent1 001 bin = manual command execution will target agent2 010 bin = manual command execution will target agent3 011 bin = manual command execution will target agent4 100 bin = manual command execution will target agent5 101 bin = manual command execution will target agent6 110 bin = manual command execution will target agent7 111 bin = manual command execution will target agent8 mm2 (manual mode 2) - bank 3 address 1c hex bit 7 6 5 4 3 2 1 0 name reserved reserved peci2.0_cmd default 00 hex bit description 7 reserved.
w83795g/adg - 131 ? aug/2/2010 revision 1.41 bit description 6 reserved. 5-0 peci2.0 command enable. (peci2.0_cmd) w83795g/adg supports peci2.0 commands. if manual mode command enable, it will be clear while relative commands are finished. bit 5 is applies for ping() command. bit 4 is applies for getdib() command. bit 3 is applies for gettemp() command. bit 2 is applies for pciwr() command. bit 1 is applies for pcird() command. bit 0 is applies for mailbox() command. when bit is set 1, the command is enabled. udcc (user defined command code) - bank 3 address 1d hex bit 7 6 5 4 3 2 1 0 name command_code[7:0] default 00 hex bit description 7-0 command_code [7:0] if auto bit is set to 1, user can?t defi ne, peci host will send relative command code. if auto bit is set to 0, user can define co mmand code to get peci command. the client address, write length and read length are defined by peci2.0_cmd (bank 3 address 1c hex bit 5-0) 12.8 peci agent tbase temperature registers (patb) location: patb1 - bank 3 address 20 hex patb2 - bank 3 address 21 hex patb3 - bank 3 address 22 hex patb4 - bank 3 address 23 hex patb5 - bank 3 address 24 hex patb6 - bank 3 address 25 hex patb7 - bank 3 address 26 hex patb8 - bank 3 address 27 hex type: read / write
w83795g/adg - 132 ? aug/2/2010 revision 1.41 reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. patb1 ? patb8 bit 7 6 5 4 3 2 1 0 name reserved agent 1 ? agent 8 tbase temperature default 00 hex bit description 7 reserved. 6-0 agent 1 ? agent 8 tbase temperature. agent base temperature for calcul ating agent0 absolute temperature range:0~127 (note 1) 12.9 getdib command (gdc) location: gdc_dib7 - bank 3 address 30 hex gdc_dib6 - bank 3 address 31 hex gdc_dib5 - bank 3 address 32 hex gdc_dib4 - bank 3 address 33 hex gdc_dib3 - bank 3 address 34 hex gdc_dib2 - bank 3 address 35 hex gdc_dib1 - bank 3 address 36 hex gdc_dib0 - bank 3 address 37 hex dib0 bit2 includes agent?s information of the domain number dib1 includes agent?s information of peci version type: read only reset: 3vsb rising, gdc_dib7 ? gdc_dib0 bit 7 6 5 4 3 2 1 0 name getdib() command read back data default 00 hex
w83795g/adg - 133 ? aug/2/2010 revision 1.41 12.10 agent characteristic registers (acr) location: acr1 - bank 3 address 38 hex acr2 - bank 3 address 39 hex acr3 - bank 3 address 3a hex type: read only reset: 3vsb rising, record which agent is able to respond to ping() command. acr1 bit 7 6 5 4 3 2 1 0 name alive_agt[7:0] default ff hex bit description 7-0 alive_agt[7:0] result of ping() command. 1: agent is able to respond to ping() command. agent is alive. 0: agent isn?t able to respond to ping() command. agent is not alive. acr2 bit 7 6 5 4 3 2 1 0 name dmn1_agt[7:0] default 00 hex bit description 7-0 dmn1_agt[7:0] result of getdib command. peci host will run according to this informat ion before register alivedmn1_agt have been programmed. indicate that which agent is with domain1. 1: agent with domain1 0: agent without domain1 acr3 bit 7 6 5 4 3 2 1 0 name vern20_agt[7:0]
w83795g/adg - 134 ? aug/2/2010 revision 1.41 default 00 hex bit description 7-0 vern20_agt[7:0] result of getdib command. peci host will run according to this informat ion before register alivedmn1_agt have been programmed. indicate which agent supports peci2.0 version. 1: support (agent?s version is peci 2.0) 0: non support (agent?s version is peci 1.0 or peci 1.1) 12.11 agent relative temperature registers (artr) these registers return the raw data retrieved from peci gettemp(). the data may be the error code (range: 8000h~81ffh) or relative temperatures to process the defined tbase . the error code will only be update in artr and absolute temperature will not be updated when the error code is received. if the rthigh mechanism is activated, the normal temperatur e will always be returned first. in case both 2 domains return errors, the return priority will be overflow error > underflow error > missing diode > general error. the reset value is 8001 hex, in that peci is defaulted to be off. in peci, 8001 hex means the diode is missing. location: a1d0rth - bank 3 address 40 hex a1d0rtl - bank 3 address 41 hex a1d1rth - bank 3 address 42 hex a1d1rtl - bank 3 address 43 hex a2d0rth - bank 3 address 44 hex a2d0rtl - bank 3 address 45 hex a2d1rth - bank 3 address 46 hex a2d1rtl - bank 3 address 47 hex a3d0rth - bank 3 address 48 hex a3d0rtl - bank 3 address 49 hex a3d1rth - bank 3 address 4a hex a3d1rtl - bank 3 address 4b hex a4d0rth - bank 3 address 4c hex a4d0rtl - bank 3 address 4d hex a4d1rth - bank 3 address 4e hex a4d1rtl - bank 3 address 4f hex a5d0rth - bank 3 address 50 hex a5d0rtl - bank 3 address 51 hex a5d1rth - bank 3 address 52 hex a5d1rtl - bank 3 address 53 hex a6d0rth - bank 3 address 54 hex a6d0rtl - bank 3 address 55 hex
w83795g/adg - 135 ? aug/2/2010 revision 1.41 a6d1rth - bank 3 address 56 hex a6d1rtl - bank 3 address 57 hex a7d0rth - bank 3 address 58 hex a7d0rtl - bank 3 address 59 hex a7d1rth - bank 3 address 5a hex a7d1rtl - bank 3 address 5b hex a8d0rth - bank 3 address 5c hex a8d0rtl - bank 3 address 5d hex a8d1rth - bank 3 address 5e hex a8d1rtl - bank 3 address 5f hex type: read only reset: 3vsb rising, bit 15 14 13 12 11 10 9 8 a1d0rth ? a8d0rth : agent 1- agent 8 domain0 relative temperature high byte a1d1rth ? a8d1rth : agent 1- agent 8 domain1 relative temperature high byte refer the peci temperature format to calculate temperature data. name sign temperature[8:2] default f8 hex bit 7 6 5 4 3 2 1 0 a1d0rtl ? a8d0rtl : agent 1- agent 8 domain0 relative temperature low byte a1d1rtl ? a8d1rtl : agent 1- agent 8 domain1 relative temperature low byte refer the peci temperature format to calculate temperature data. name temperature[1:0] temp_2 temp _4 temp_8 temp_16 temp_32 temp_64 default 80 hex gettemp() peci temperature format: bit description 15 sign bit. (sign) in peci protocol, this bit should always be 1 to represent a negative temperature. 14-6 the integer part of the relative temperature. ( temperature[8:0] ) 5 temp_2. 0.5 unit. 4 temp_4. 0.25 unit. 3 temp_8. 0.125 unit. 2 temp_16 . 0.0625 unit. 1 temp_32 . 0.03125 unit. 0 temp_64 . 0.015625 unit.
w83795g/adg - 136 ? aug/2/2010 revision 1.41 gettemp() response definition: response meaning general sensor error (gse) thermal scan did not complete in time. retry is appropriate. 0x0000 processor is running at its maximum te mperature or is currently being reset. all other data valid temperature reading, reported as a negative offset from the tcc activation temperature. the valide temperature reading is referred to gettemp() peci temperature format on some occasions, peci will re turn the abnormal states of the peci bus in addition to the temperature. all the information will be recorded. in some cases, the w83795 g/adg will also do further processing for the alert mechanism. the following describes these codes and their effects to the w83795g/adg. error code description w83795g/adg host operation 8000 hex general sensor error 8001 hex sensing device missing no further processing. 8002 hex operational, but the temperature is lower than the sensor operation range. compulsorily write 0 back to the temperature readouts.(bank 0 index 1c hex ~ 1f hex ) 8003 hex operational, but the temperature is higher than the sensor operation range. compulsorily write 127 back to the temperature readouts.(bank 0 index 1c hex ~ 1f hex ) 8004 hex ? 81ff hex reserved. no further operation. besides error conditions or invalid fcs, the normal temp erature will be written back to temperature readouts with the sum of artr value and tbase value. 12.12 agent tcontrol temperature registers (attr) location: a1tth - bank 3 address 60 hex a1ttl - bank 3 address 61 hex a2tth - bank 3 address 62 hex a2ttl - bank 3 address 63 hex a3tth - bank 3 address 64 hex a3ttl - bank 3 address 65 hex a4tth - bank 3 address 66 hex a4ttl - bank 3 address 67 hex a5tth - bank 3 address 68 hex a5ttl - bank 3 address 69 hex a6tth - bank 3 address 6a hex
w83795g/adg - 137 ? aug/2/2010 revision 1.41 a6ttl - bank 3 address 6b hex a7tth - bank 3 address 6c hex a7ttl - bank 3 address 6d hex a8tth - bank 3 address 6e hex a8ttl - bank 3 address 6f hex type: read only reset: 3vsb rising, bit 15 14 13 12 11 10 9 8 a1tth ? a8tth : agent 1- agent 8 tcontrol temperature high byte refer the peci temperature format to calculate temperature data. name sign temperature[8:2] default fd hex bit 7 6 5 4 3 2 1 0 a1ttl ? a1ttl : agent 1- agent 8 tcontr ol temperature low byte refer the peci temperature format to calculate temperature data. name temperature[1:0] temp_2 temp _4 temp_8 temp_16 temp_32 temp_64 default 80 hex 12.13 pci configuration address registers (pcar) refer to pci configuration address defined format to set pc address4 ? pc address1 registers value for pciconfigrd() or pciconfwr() command. pci bus address assignment type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. location: pc address4 (msb) - bank 3 address 70 hex pc address3 - bank 3 address 71 hex pc address2 - bank 3 address 72 hex pc address1 (lsb) - bank 3 address 73 hex bit pci configuration address [31:0]
w83795g/adg - 138 ? aug/2/2010 revision 1.41 name pc address4 pc address3 pc address2 pc address1 default 00 hex 00 hex 00 hex 00 hex pci configuration address defined format: bit description 31-28 reserved. 27-20 bus 19-15 device 14-12 function 11 - 0 register 12.14 pci configuration write data (pcwd) type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. location: pcw data4 (msb) - bank 3 address 74 hex pcw data3 - bank 3 address 75 hex pcw data2 - bank 3 address 76 hex pcw data1 (lsb) - bank 3 address 77 hex bit pci configuration write data [31:0] name pcw data4 pcw data3 pcw data2 pcw data1 default 00 hex 00 hex 00 hex 00 hex pciconfigwr() response definition: ?cc? indicates completion code. response meaning bad fcs electrical error or assured write fcs (aw fcs) failure. abort fcs illegal command formatting (mismatched rl/wl/command code) cc: 0x40 command passed, data is valid. cc: 0x80 error causing a response timeout. either due to a rare, internal timing condition or a processor reset conditi on or processor s1 state. retry is appropriate outside of the reset or s1 states.
w83795g/adg - 139 ? aug/2/2010 revision 1.41 12.15 pci configuration read data (pcrd) type: read only reset: 3vsb rising, location: pcr data4 (msb) - bank 3 address 78 hex pcr data3 - bank 3 address 79 hex pcr data2 - bank 3 address 7a hex pcr data1 (lsb) - bank 3 address 7b hex bit pci configuration read data [31:0] name pcr data4 pcr data3 pcr data2 pcr data1 default 00 hex 00 hex 00 hex 00 hex pciconfigrd() response definition: ?cc? indicates completion code. response meaning abort fcs illegal command formatting (mismatched rl/wl/command code) cc: 0x40 command passed, data is valid. cc: 0x80 error causing a response timeout. either due to a rare, internal timing condition or a processor reset conditi on or processor s1 state. retry is appropriate outside of the reset or s1 states. 12.16 mbxsend command (msc) type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. location: mbxsend request type - bank 3 address 80 hex bit 7 6 5 4 3 2 1 0 name mbxsend request type default 00 hex location: mbxsend data4 (msb) - bank 3 address 81 hex mbxsend data3 - bank 3 address 82 hex mbxsend data2 - bank 3 address 83 hex mbxsend data1 (lsb) - bank 3 address 84 hex
w83795g/adg - 140 ? aug/2/2010 revision 1.41 bit mbxsend data [31:0] name mbxsend data4 mbxsend data3 mbxsend data2 mbxsend data1 default 00 hex 00 hex 00 hex 00 hex mbxsend() response definition: ?cc? indicates completion code. response meaning bad fcs electrical error. cc: 0x80 error causing a response timeout. either due to a rare, internal timing condition or a processor reset conditi on or processor s1 state. retry is appropriate outside of the reset or s1 states. cc: 0x86 mailbox interface is unavailable or busy. 12.17 completion code (cc) location: cc - bank 3 address 85 hex type: read only reset: 3vsb rising, bit 7 6 5 4 3 2 1 0 name completion code default 00 hex 12.18 mbxget command (mgc) type: read only reset: 3vsb rising, location: mbxget data4 (msb) - bank 3 address 86 hex mbxget data3 - bank 3 address 87 hex mbxget data2 - bank 3 address 88 hex mbxget data1 (lsb) - bank 3 address 89 hex bit mbxget data [31:0] name mbxget data4 mbxget data3 mbxget data2 mbxget data1 default 00 hex 00 hex 00 hex 00 hex mbxget transaction id - bank 3 address 8a bit 7 6 5 4 3 2 1 0
w83795g/adg - 141 ? aug/2/2010 revision 1.41 name reserved transaction id default 00 hex mbxget() response definition: ?cc? indicates completion code. response meaning abort write fcs response data is not ready. command retry is appropriate. cc: 0x40 command passed, data is valid. cc: 0x80 error causing a response timeout. either due to a rare, internal timing condition or a processor reset conditi on or processor s1 state. retry is appropriate outside of the reset or s1 states. cc: 0x81 thermal configuration data was malformed or exceeded limits. cc: 0x82 thermal status mask is illegal. cc: 0x83 invalid counter select. cc: 0x85 failure due to lack of mailbox lock or invalid transaction id. cc: 0x86 mailbox interface is unavailable or busy. 12.19 sb-tsi configuration register (stcr) location: stcr - bank 3 address a0 hex type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. stcr bit 7 6 5 4 3 2 1 0 name reserved fsb_tsi[3:0] sthe default 10 hex bit description 7-5 reserved. 4-1 set the frequency of sb-tsi scl ( fsb_tsi[3:0] ) sb-tsi scl frequency is 225khz / (fsb_tsi [3:0] +1). note that fsb_tsi[3:0] can not be set to 000 bin. 0 sb-tsi host enable. ( sthe ) if digital temperature sensor enable ( dtse ) = 1 & dts interface select ( dis ) = 1, sb-tsi
w83795g/adg - 142 ? aug/2/2010 revision 1.41 host function will be enabled and sb-tsi host enable ( sthe) will be set to 1. this bit is read only. 12.20 sb-tsi auto read period (starp) location: starp - bank 3 address a1 hex type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. starp bit 7 6 5 4 3 2 1 0 name tsiautoreadcycle[7:0] default 19 hex bit description 7-0 sb-tsi auto read cycle ( tsiautoreadcycle[7:0] ) tp = 1ms * tsiautoreadcycle[7:0] sb-tsi host will read one slave's temperature in tp time. note that tsiautoreadcycle[7:0] can not set to 00 hex 12.21 sb-tsi slave enable (stse) location: stse - bank 3 address a2 hex type: read only reset: 3vsb rising, stse bit 7 6 5 4 3 2 1 0 name stse8 stse7 stse6 stse5 stse4 stse3 stse2 stse1 default 00 hex bit description 7-0 sb-tsi dts8 ? dts1 enable (stse8-stse1)
w83795g/adg - 143 ? aug/2/2010 revision 1.41 bit description 0 = disable. (default) 1 = enable. if digital temperature sensor enable ( dtse ) = 1 & dts interface select ( dis ) = 1, sb-tsi slave address will be enabled and sb-tsi dts8 ? dts1 enable (stse8-stse1) will be set to 1. in amd sb-tsi, dts1 slave address is 98h. dts2 slave address is 9ah. dts3 slave address is 9ch. dts4 slave address is 9eh. dts5 slave address is 90h. dts6 slave address is 92h. dts7 slave address is 94h. dts8 slave address is 96h. this register is read only. 12.22 sb-tsi one shot start register (stoss) location: stoss - bank 3 address a3 hex type: read / write reset: 3vsb rising, init reset (cr01.bit7) is set, 3vdd rising @ rst_vdd_md (cr01.bit5) set, sysrstin# falling @ sysrst_md (cr01.bit6) set. stoss bit 7 6 5 4 3 2 1 0 name reserved oneshot default 00 hex bit description 7-1 reserved. 0 sb-tsi one shot start ( oneshot ). 0 = this bit will return 0 when sb-tsi host finished one shot start sb-tsi command. 1 = writing a 1 to this bit, sb-tsi host will one shot start sb-tsi command. 12.23 sb-tsi manual mode configuration registers (stmmcr) type: read / write
w83795g/adg - 144 ? aug/2/2010 revision 1.41 reset: 3vsb rising, 3vdd rising @ rst_vdd_md (cr01.bit5) set. stmmcr1 - bank 3 address a4 hex bit 7 6 5 4 3 2 1 0 name mme ose reserved rwc default 01 hex bit description 7 sb-tsi manual mode enable. ( mme ) 0 = disable. (default) 1 = enable. 6 sb-tsi one shot enable. (ose) 0 = disable. (default) 1 = enable. 5-1 reserved. 0 set sb-tsi read / write command (rwc) 0 = write command. 1 = read command. (default) bit[7:6] mme ose meaning 0 0 sb-tsi host always read sb-tsi 01h and sb-tsi 10h command code data continually and stored in the bank0 dts1~8 and vr lsb registers. 0 1 after writing a 1 to sb-tsi one shot start ( oneshot ), sb-tsi host read one time sb-tsi 01h and sb-tsi 10h command code data and stored in the bank0 dts1~8 and vr lsb registers. 1 0 after writing a 1 to sb-tsi one shot start ( oneshot ), sb-tsi host read or write one time the data and stored in the sb-tsi read data high byte ( strd) register. the data command code will depend on sb-tsi command code ( stcc ) register. stmmcr2 - bank 3 address a5 hex bit 7 6 5 4 3 2 1 0 name stcc default 01 hex bit description
w83795g/adg - 145 ? aug/2/2010 revision 1.41 bit description 7 -0 sb-tsi command code. ( stcc ) refer the amd sb-tsi specification to set command code. 01 hex = cpu temperature high byte register. 02 hex = sb-tsi status register. 03 hex = sb-tsi configuration register. 04 hex = update rate register. 07 hex = high temperature threshold high byte register. 08 hex = low temperature threshold high byte register. 09 hex = sb-tsi configuration register. 10 hex = cpu temperature low byte register. 11 hex = cpu temperature offset high byte register. 12 hex = cpu temperature offset low byte register. 13 hex = high temperature threshold low byte register. 14 hex = low temperature threshold low byte register. 22 hex = timeout configuration register. 32 hex = alert threshold register. bf hex = alert configuration register. fe hex = manufacture id register. ff hex = sb-tsi revision register. stmmcr3 - bank 3 address a6 hex bit 7 6 5 4 3 2 1 0 name sb-tsi write data default 00 hex 12.24 sb-tsi read data (strd) location: strd - bank 3 address a8 hex type: read only reset: 3vsb rising, strd bit 7 6 5 4 3 2 1 0 name sb-tsi read data byte of manual mode. if read data are indicated to temperature, refer the table-1 sb-tsi temperature encoding example to calculate temperature data. default 00 hex
w83795g/adg - 146 ? aug/2/2010 revision 1.41 13. electrical characteristics 13.1 absolute maximum ratings parameter rating unit power supply voltage -0.3 to +3.6 v input voltage -0.3 to +3.6 v operating temperature 0 to +70 c storage temperature -55 to +150 c 13.2 dc characteristics (ta = 0 c to 70 c, 3vdd = 3.3v 10%, 3vsb =3.3v 10%, gnd = 0v) parameter sym. min. typ. max. unit conditions od 12 ? open-drain output pin with source-sink capability of 12 ma output low voltage v ol 0.4 v i ol = 12 ma out 12 - output buffer pin with source-sink capab ility of 12 ma output low voltage v ol 0.4 v i ol = 12 ma output high voltage v oh 2.4 v i oh = -12 ma v1 - vid input pin for intel tm vrm design input low voltage v il 0.4 v input high voltage v ih 0.6 v v2 - vid input pin for amd tm vrm design input low voltage v il 0.8 v input high voltage v ih 1.4 v v3 ?bi-direction pin for amd tm svid design input low voltage v il 0.6 v
w83795g/adg - 147 ? aug/2/2010 revision 1.41 parameter sym. min. typ. max. unit conditions input high voltage v ih 1 v output low voltage v ol 0.285 v v4 ? bi-direction pin for intel tm peci input low voltage v il 0.275v tt 0.5v tt v input high voltage v ih 0.55v tt 0.725v tt v output low voltage v ol 0.25v tt v output high voltage v oh 0.75v tt v hysterisis v hys 0.1v tt v v5 ? bi-direction pin for prochot input low voltage v il 0.4 v input high voltage v ih 0.8 v output low voltage v ol 0.2 v in ts - ttl level schmitt-triggered input pin input low voltage v il 0.8 v 3vsb = 3.3v input high voltage v ih 2.0 v 3vsb = 3.3v input high leakage i lih +10 a vin=3.3v input low leakage i lil -10 a vin=0v ain - analog input pin input high leakage i lih +1 a vin=3.3v input low leakage i lil -1 a vin=0v
w83795g/adg - 148 ? aug/2/2010 revision 1.41 13.3 ac characteristics smbus interface valid data scl sda in sda out t hd;sda t scl t su;dat t su;sto serial bus timing diagram t r t r t hd;dat parameter symbol min. max. unit scl clock period t - scl 10 us start condition hold time t hd;sda 4.0 us stop condition setup-up time t su;sto 4.0 us data to scl setup time t su;dat 150 ns data to scl hold time t hd;dat 270 ns scl and sda rise time t r 1.0 us scl and sda fall time t f 300 ns clock input timing clkin description min typ max clock cycle time (1/clkin) x0.97 1/clkin (1/clkin) x1.03 duty cycle 45% 55%
w83795g/adg - 149 ? aug/2/2010 revision 1.41 14. order information part no. package remarks w83795g 64-pin lqfp pb-free package W83795ADG 48-pin lqfp pb-free package
w83795g/adg - 150 ? aug/2/2010 revision 1.41 15. top marking specifications first line nuvoton logo, and company name. second line ic part number: w83795g W83795ADG third line serial number forth line tracking code: 8 14 g a ba for package information 8 package is made in 2008 14 week: 14 g assembly house id; g means greatek; a means ase; o means ose a ic version; a means a version; b means b version; c means c version ba mask version inbond w83795g 28201234 814gaba
w83795g/adg - 151 ? aug/2/2010 revision 1.41 16. package drawing and dimensi ons w83795g (64-pin lqfp 10x10x1.4mm) 0 7 0 1.00 0.75 0.60 12.00 0.45 0.039 0.030 0.024 0.472 0.018 0.50 0.20 0.27 1.45 1.60 10.00 1.40 0.09 0.17 1.35 0.05 0.008 0.011 0.057 0.063 0.393 0.055 0.020 0.004 0.007 0.053 0.002 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.008 0.20 7 0.393 10.00 0.472 12.00 0.006 0.15 0.004 0.10 3.5 3.5
w83795g/adg - 152 ? aug/2/2010 revision 1.41 W83795ADG (48-pin lqfp)
w83795g/adg - 153 ? aug/2/2010 revision 1.41 17. revision history version date page description 1.0 12/12/2008 n.a. the initial formal release. 1.1 05/05/2009 147 added dc characteristic and revised typos. 1.2 06/03/2009 17,25,126,149 1. modified clkin pin description. 2. modified peci atr register. 3. added clkin specification. 1.3 10/21/2009 32,108,129 1. added c version chip information. 2. modified pwm fan output prescalar default value. 3. added peci read value clamping function. 4. revised typos in the document. 1.4 6/3/2010 61~64,148 1. revised register description of prochot. 2. modified ac characteristic. 3. revised typos in the document. 1.41 8/2/2010 51 1. modified the smi_pol description.
w83795g/adg - 154 ? aug/2/2010 revision 1.41 important notice nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical im plantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. furthermore, nuvoton products are not intended for applications wherein failure of nuvoton products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify nuvoton for any damages resulting from such improper use or sales.

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